This article proposes a high-gain and low-power low-noise amplifier (LNA) by adopting a simultaneous noise- and input-matched (SNIM) maximum achievable gain ( G _max ) core. The G _max -core is implemented by adjusting the infinite combinations of embedding networks with three passive elements. Based on the proposed two-port noise analysis for implementing the G _max -core, the input stage G _max -core can achieve a simultaneous power gain and noise matching. The adoption of the G _max -core in the input stage can maximize the amount of gain per stage, leading to higher total power gain and lower noise figure (NF). The two-stage 150-GHz LNA adopting the SNIM G _max -core is implemented in a 65-nm CMOS process. The measurement results show a peak gain of 17.9 dB at 152.2 GHz, 3-dB bandwidth of 11 GHz, NF of 4.7 and 6.2 dB at 148 and 150 GHz, respectively, and a peak power added efficiency (PAE) of 7.7% while dissipating only 13.73 mW. This work shows the highest gain per stage and the lowest NF with the lowest dc power consumption among other reported CMOS D-band amplifiers.

This paper presents a Colpitts oscillator-based self-starting boost converter for thermoelectric energy harvesting. An enhanced swing Colpitts oscillator with a 10-stage voltage multiplier is adopted as a startup circuit so that the minimum startup voltage of 40 mV is achieved. As a main converter, a zero-current-switching boost converter with a dead time controller achieves the maximum end-to-end efficiency of 75%. The inductor used in the Colpitts oscillator is reused in the main boost converter to minimize the use of the inductor. Implemented in a 65-nm CMOS, the proposed converter that requires only two external inductors provides a regulated output voltage of 1.1 V from a thermoelectric generator with an internal resistance of 2.2 $\Omega$ over the input range of 40–200 mV.

This paper presents a reconfigurable dc–dc converter for maximum thermoelectric generator (TEG) energy harvesting in a battery-powered duty-cycling wireless sensor node. The proposed dc–dc converter adopts discontinuous energy harvesting, which operates in single-input dual-output (SIDO) boost, battery-TEG pile-up buck (BTPB), dual-phase buck–boost (DPBB), and battery supplied buck modes with a single shared inductor. Fabricated in a 65-nm CMOS process, the converter adopts an adaptive dead-time controller for zero-voltage switching (ZVS) and an adaptive switch size (ASS) with maximum power point tracking (MPPT) to maximize efficiency in a wide TEG voltage range. The SIDO boost mode achieves 88.5% and 81.1% peak end-to-end efficiency with maximum and no-load conditions (only charging the battery), respectively. The combination of BTPB and DPBB modes to maximize the TEG power extraction during the battery-powered operation results in up to 44% saving in battery power. The battery-supplied buck mode achieves 93.3% peak efficiency.

This letter reports the design of terahertz amplifiers using the concept of maximum achievable gain (Gmax) of a transistor embedded in a linear, lossless, reciprocal network. Implemented in a 65-nm CMOS, by adopting the optimized Gmax-core, 280- and 300-GHz amplifiers achieve peak gain of 12 and 9 dB, peak power-added efficiency (PAE) of 1.6% and 1.4%, and gain per stage of 4 and 3 dB, respectively, while dissipating 17.9 mW, which is the best performance up to date in terms of operating frequency, gain per stage, and PAE in CMOS process.

The nonresonant THz response of CMOS FET has been analyzed based on static nonlinearities of the transistor channel. For the applied gate-to-source and drain-to-source signals, the significance of the second-order nonlinear terms is investigated as a function of dc bias conditions. A cross-coupled design for differential excitation of the THz detector is also proposed, and it has been shown, based on analysis as well as through measurements, that a cross-coupled detector topology can give the highest responsivity in an unbiased-drain operation, among the possible detector topologies. A minimum optical noise equivalent power (NEP) of $\text{29 pW}/\surd \text{Hz}$ is measured for the cross-coupled detector topology at 500 GHz with unbiased drain. The change in the polarity of the detector response under certain bias conditions is also explained. This paper gives a comprehensive picture of the behavior of the CMOS THz detector by discussing the design considerations such as readout modes, optimum bias points, and device dimensions with respect to both responsivity and NEP.