This letter reports the design of terahertz amplifiers using the concept of maximum achievable gain (Gmax) of a transistor embedded in a linear, lossless, reciprocal network. Implemented in a 65-nm CMOS, by adopting the optimized Gmax-core, 280- and 300-GHz amplifiers achieve peak gain of 12 and 9 dB, peak power-added efficiency (PAE) of 1.6% and 1.4%, and gain per stage of 4 and 3 dB, respectively, while dissipating 17.9 mW, which is the best performance up to date in terms of operating frequency, gain per stage, and PAE in CMOS process.

This paper presents a reconfigurable SRAM-based physically unclonable function (PUF) topology with multiple challenge-response pairs (CRPs) per cell. The proposed PUF structure enables a very large CRP space by connecting additional pull-up and pull-down paths to each SRAM cell. These alternate pathways to the supply rail and ground are activated by the challenge inputs, which effectively reconfigure the transfer characteristics of each cross-coupled inverter. A newly proposed response instability detector improves bit error rate (BER) performance by discarding unstable response. In addition, the proposed PUF adds indirect challenges by scrambling the responses using a Galois linear feedback shift register (LFSR). The proposed PUF can be applied to a wider range of applications as a CRP PUF because it has multiple CRPs in addition to the small area and fast operating speed, which are the advantages of the conventional SRAM structure. In order to verify the performance of the proposed architecture, a 32×32-bit reconfigurable SRAM PUF array with 32-bit challenge is implemented in a 65 nm CMOS process. Experimental results show a core area of 88.867 μ m ² /bit, energy efficiency of 0.082 pJ/bit, and inter-chip Hamming distance (HD) of 48.93% across 40 chips. By applying an unstable bit discard (UBD) scheme, BER is improved from 13.7% to 0.9%. Compared to the state-of-the-art, the proposed PUF is shown to be highly competitive in area, throughput and energy efficiency.

This article reports the concept of a double maximum achievable gain (double- $G_{\mathrm{ max}}$ ) core for the implementation of sub-terahertz high-gain amplifier design. The double- $G_{\mathrm{ max}}$ core is a $G_{\mathrm{ max}}$ core that adopts another linear, lossless, and reciprocal network that satisfies the $G_{\mathrm{ max}}$ condition onto an even number of cascaded transistor-level $G_{\mathrm{ max}}$ cores. It is shown that the double- $G_{\mathrm{ max}}$ core, due to its regenerative nature, can achieve much higher gain per stage than that of the same number of cascaded $G_{\mathrm{ max}}$ cores while satisfying the unconditional stability. Implemented in a 65-nm CMOS process, by adopting the proposed double- $G_{\mathrm{ max}}$ core, 247- and 272-GHz two-stage amplifiers achieve the peak gain of 18 and 15 dB, the gain per stage of 9 and 7.5 dB, and the PAE of 4.44% and 2.37%, respectively, while dissipating 21.5 mW.

This paper presents an ultra-small physical unclonable function (PUF) chip structure to protect data in compact IoT sensor devices. The proposed PUF has far fewer transistors and a reduced active area compared to the conventional strong PUF with multiple challenge response pairs (CRPs). According to the manufacturing process variations, the conventional SRAM-based PUF uses a switching transistor and a main transistor to implement multiple CRPs, whereas the proposed structure adds the function of a switching transistor to a single main transistor, controlling the body voltage to switch the transistor. This unified and simple PUF structure results in significant silicon area reduction. For a PUF with a 32-bit challenge, the number of transistors is significantly reduced by 40%; the active area of the conventional structure is $57.78~\mu m^{2}$ while the area of the proposed structure is $36.4~\mu m^{2}$ . Overall, an active area reduction of 38% is realized with the same number of CRPs. Here, we implemented an SRAM-based PUF system with a 32-bit challenge, a 1024-bit response, and 160 million CRPs. PUF core cell shows energy efficiency of 0.09 pJ/bit. The inter-Hamming distance is 48.89%, while the intra-Hamming distance is 1.2% after data post-processing, i.e., discarding unstable bits. A prototype chip is implemented in the 65nm CMOS process with a supply voltage of 1.2V. Compared to the prior arts, the proposed prototype is shown effective silicon area reduction while maintaining remarkable energy efficiency.

This article presents a high fundamental frequency subterahertz (sub-THz) CMOS oscillator with a single core. The proposed structure with a capacitive load reduction circuit increases the fundamental oscillation frequency by decreasing the parasitic capacitances of the buffer transistor and inductor and minimizing the loss caused by the gate resistance of the buffer stage. To achieve high output power, the proposed oscillator combines the differential output signals through a differential-to-single (DTS) transformer. A push-push oscillator based on the high fundamental frequency oscillator is also introduced to increase the operating frequency further. The proposed oscillators are implemented in a 65-nm CMOS process. Measurements of the fundamental oscillator reveal an output power of 0.285 mW at 251 GHz, while consuming 21 mA from a 1.3-V supply voltage. The measured operating frequency of the push-push oscillator is 432 GHz.