This letter reports the design of terahertz amplifiers using the concept of maximum achievable gain (Gmax) of a transistor embedded in a linear, lossless, reciprocal network. Implemented in a 65-nm CMOS, by adopting the optimized Gmax-core, 280- and 300-GHz amplifiers achieve peak gain of 12 and 9 dB, peak power-added efficiency (PAE) of 1.6% and 1.4%, and gain per stage of 4 and 3 dB, respectively, while dissipating 17.9 mW, which is the best performance up to date in terms of operating frequency, gain per stage, and PAE in CMOS process.

This article reports the concept of a double maximum achievable gain (double- $G_{\mathrm{ max}}$ ) core for the implementation of sub-terahertz high-gain amplifier design. The double- $G_{\mathrm{ max}}$ core is a $G_{\mathrm{ max}}$ core that adopts another linear, lossless, and reciprocal network that satisfies the $G_{\mathrm{ max}}$ condition onto an even number of cascaded transistor-level $G_{\mathrm{ max}}$ cores. It is shown that the double- $G_{\mathrm{ max}}$ core, due to its regenerative nature, can achieve much higher gain per stage than that of the same number of cascaded $G_{\mathrm{ max}}$ cores while satisfying the unconditional stability. Implemented in a 65-nm CMOS process, by adopting the proposed double- $G_{\mathrm{ max}}$ core, 247- and 272-GHz two-stage amplifiers achieve the peak gain of 18 and 15 dB, the gain per stage of 9 and 7.5 dB, and the PAE of 4.44% and 2.37%, respectively, while dissipating 21.5 mW.

This paper proposes a simultaneous output power- and gain-matching technique in a sub-THz power amplifier (PA) design based on a maximum achievable gain ( G _max ) core. The optimum combination of three-passive-elements-based embedding networks for implementing the G _max -core is chosen considering the small- and large-signal performances at the same time. By adopting the proposed technique, the simultaneous output power- and gain-matching can be achieved, maximizing the small-signal power gain and large-signal output power simultaneously. A 150 GHz single-ended two-stage PA without power combining circuit is implemented in a 65-nm CMOS process based on the proposed technique. The amplifier achieves a peak power gain of 17.5 dB, peak power added efficiency (PAE) of 13.3 and 16.1 %, saturated output power ( P _sat ) of 10.3 and 9.4 dBm, and DC power consumption of 86.3 and 52.4 mW, respectively, under the bias voltage of 1.2 and 1 V, which corresponds to the highest PAE, gain per stage and P _out per single transistor among other reported CMOS D-band PAs.

The frequency multiplier with broadband frequency divide-by-2 followed by wide locking-range frequency tripler is presented in this article. The frequency divide-by-2 provides the quadrature signals with good mismatch performance across the entire operating frequency. The frequency tripler is quadrature locked while providing high fundamental tone rejection. The notch filtering with the source degeneration removes the harmonic tone due to the injected signal from the frequency divide-by-2 and minimizes the signal loss at the desired output frequency without additional current consumption. The proposed notch filter embedded within the injection-locked frequency tripler (ILFT) decouples the strict tradeoff between the selectivity (harmonic rejection) and the locking range, and thus enables the optimization of both parameters simultaneously. Quadrature outputs maintain good quadrature relations across the wide locking range based on the proposed layout and injection methods. The proposed circuit is fabricated in 45-nm CMOS technology. From the measurement result, the frequency multiplier achieves 25.61 dBc of harmonic rejection ratio without any additional bandpass filtering stages and exhibits the 57.6% of locking range corresponding to 20.4-36.6-GHz output frequency in the locked condition. The frequency multiplier with a multiplication ratio of 1.5 consumes 68 mA and occupies only 490 μ m x 560 μ m of chip-area operated from the 1.2 V of supply voltage.