In this paper, simulation-based research on the electrostatics of Pi-gate silicon-on-insulator (SOI) MOSFETs is carried out. To do so, a 2-D self-consistent Schrodinger-Poisson solver has been implemented. The inclusion of the quantum effects has been demonstrated to be necessary for the accurate simulation of these devices in the nanometer range. Specifically, this paper is focused on the corner effects in multiple-gate SOI MOSFETs, defined as the formation of independent channels with different threshold voltages. Corner effects are studied as a function of different parameters, such as the doping density, silicon-fin dimensions, corner rounding, and gate oxide thickness. Finally, the relation between corner effects and the transition from a fully to a partially depleted body is analyzed.

We show the importance of acoustic phonon confinement in ultrathin silicon-on-insulator inversion layers by comparing electron mobility calculated by the Monte Carlo method assuming a bulk acoustic phonon model (the usual procedure) with that obtained by using a confined acoustic phonon model developed in this work. Both freestanding and rigid boundary conditions are taken into account for the evaluation of the confined phonon dispersion in a three-layer structure. Mobility reductions of 30% are observed for silicon thicknesses of around $5–10\mathrm{nm}$ when the confined acoustic phonon model is used.

2-D numerical simulations are used to demonstrate the Z²-FET as a competitive embedded capacitor-less dynamic random access memory cell for low-power applications. Experimental results in 28-nm fully depleted-silicon on insulator technology are used to validate the simulations prior to downscaling tests. Default scaling, without any structure optimization, and enhanced scaling scenarios are considered before comparing the bit cell area consumption and integration density with other eDRAM cells in the literature.

The trend toward continuous integration of the nanometer scale and the rise of nonconventional device concepts such as multigate transistors present important challenges for the semiconductor community. Simulation tools have to be adapted to this new scenario where classical approaches are not sufficiently accurate, and quantum effects have to be taken into account. This paper proposes a method of including quantum corrections in Monte Carlo (MC) simulations without solving the Schroumldinger equation. The approach, based on the effective conduction band-edge (ECBE) method, considers the effects of an arbitrary effective mass tensor, describing valley characteristics and confinement directions while avoiding the use of effective mass as a fitting parameter. The performance of the multivalley ECBE method is tested using an ensemble MC simulator to study benchmark devices for next International Technology Roadmap for Semiconductors technological nodes, a 25-nm channel length bulk-MOSFET and a double-gate silicon-on-insulator MOSFET in both steady-state and transient situations