For high electron mobility transistors (HEMTs) power transistors based on AlGaN/GaN heterojunction, p-GaN gate has been the gate topology commonly used to deplete the two dimensional electron gas (2-DEG) and achieve a normally-OFF behavior. But fully recessed MIS gate GaN power transistors or MOSc-HEMTs have gained interest as normally-OFF HEMTs thanks to the wider voltage swing and reduced gate leakage current when compared to p-GaN gate HEMTs. However the mandatory AlGaN barrier etching to deplete the 2-DEG combined with the nature of the dielectric/GaN interface generates etching-related defects, traps, and roughness. As a consequence, the threshold voltage (V_TH) can be unstable, and the electron mobility is reduced, which presents a challenge for the integration of a fully recessed MIS gate. Recent developments have been studied to solve this challenge. In this paper, we discuss developments in gate recess with low impact etching and atomic layer etching (ALE) alongside surface treatments such as wet cleaning, thermal or plasma treatment, all in the scope of having a surface close to pristine. Finally, different interfacial layers, such as AlN, and alternative dielectrics investigated to optimize the dielectric/GaN interface are presented.

This study investigated the low contact resistivity and Schottky barrier characteristics in p-GaN by modifying the thickness and doping levels of a p-InGaN cap layer. A comparative analysis with highly doped p-InGaN revealed the key mechanisms contributing to low-resistance contacts. Atomic force microscopy inspections showed that the surface roughness depends on the doping levels and cap layer thickness, with higher doping improving the surface quality. Notably, increasing the doping concentration in the p⁺⁺-InGaN cap layer significantly reduced the specific contact resistivity to 6.4 ± 0.8 × 10⁻⁶ Ω·cm², primarily through enhanced tunneling. Current–voltage (I–V) characteristics indicated that the cap layer’s surface properties and strain-induced polarization effects influenced the Schottky barrier height and reverse current. The reduction in barrier height by approximately 0.42 eV in the p⁺⁺-InGaN layer enhanced hole tunneling, further lowering the contact resistivity. Additionally, polarization-induced free charges at the metal–semiconductor interface reduced band bending, thereby enhancing carrier transport. A transition in current conduction mechanisms was also observed, shifting from recombination tunneling to space-charge-limited conduction across different voltage ranges. This research underscores the importance of doping, cap layer thickness, and polarization effects in achieving ultra-low contact resistivity, offering valuable insights for improving the performance of p-GaN-based power devices.

In this paper, we present an approach to enhance thermal dissipation of GaN on silicon high electron mobility transistors (HEMTs) and Schottky barrier diodes (SBDs). The initial silicon substrate was removed and replaced by a copper substrate using a transfer process based on polymer bonding to a temporary wafer. Electrical and thermal characterizations were performed to study the impact of the transfer. The thermal measurements showed a lower temperature for the HEMTs transferred onto a copper substrate in the case of a 1 ms pulse at 0.34 W/mm.

X-ray irradiation is performed in order to study the behavior of lateral hetero-junction Schottky diode to help predict the effect of X-ray on recessed gate HEMT based on the same process flow. The Schottky diodes are subjected to high dose rate X-ray and present a threshold voltage positive shift as well as an increase of reverse current leakage on I-V characteristics. 100°C annealing is performed, and the depth of the traps and their origin is identified through fitting of detrapping model with experimental Forward Voltage shift post-annealing. Hypothesis regarding the increased current leakage are proposed following observed I-V measurements. The obtained results will be used as basis for further studies of components with the same process flow, in order to devise a rad-hard version of components.

Today, wide bandgap (WBG) GaN semiconductors are considered the future, allowing the improvement of power transistors. The main advantage of GaN is the presence of two-dimensional electron gas (2Deg) typically used as a conduction layer in normally-on and normally-off transistors. Concerning the normally-off family, several solutions are proposed. Among these, one of the most promising is the MIS-Gate technology that features a gate recess architecture allowing the semiconductor to physically cut off the 2Deg and drastically decrease gate–source leakage currents. The Vth relaxation characteristic, after voltage stress, has been investigated. It has been shown that the main impact is due to charges close to the gate dielectric/GaN interface, precisely dwelling within the dielectric or the GaN epitaxy. This work provides an analytical model of the Vth evolution of these MIS-GATE (metal insulator semiconductor gate) transistors fabricated on GaN-silicon substrate. This model allows the extraction of different trap energy levels from a temporary threshold voltage (Vth) shift after 650 V stress. Based on this method, it is possible to identify up to four different trap energy levels. By comparing state of the art methods, we show that these obtained energy levels are well correlated with either magnesium and carbon impurity or Ga and/or N vacancy sites in the GaN epitaxy.

GaN p-channel field-effect transistors (p-FETs) are critical for enabling complementary integration of power and logic, while offering high breakdown capability. However, achieving high on-current in GaN p-FETs remains a significant challenge, primarily due to the low hole concentration, poor mobility, and challenges in forming stable, low-resistance ohmic contacts. Here, we present a novel GaN p-FET architecture that exhibits unconventional electron conduction, which helps enhance both thermal response and current modulation. We conduct a comprehensive investigation of heavily Mg-doped p⁺⁺-GaN layers, focusing on contact optimization for high-temperature operation. Structural and interfacial characterization confirms high crystal quality and a thermally robust Ni/Au contact stack stabilized by an interfacial Ni_xO_y layer. This strategic interfacial layer, combined with moderate-temperature annealing, promotes Mg activation and suppresses oxygen-related traps, resulting in a ~ 73% reduction in contact resistance. Temperature-dependent analysis further reveals non-monotonic Schottky barrier modulation driven by interface evolution. Integrated into the device, this contact strategy enables thermally enhanced operation, with a drastically increase in on-state current and threshold voltage shifting positively by ~ 69% with temperature. These findings highlight a model shift in GaN p-FET design, where interface study and transport-mode innovation enable high-performance, thermally resilient devices for next-generation power integration.