In this work, fully vertical GaN trench MOSFETs were fabricated and characterized to evaluate their electrical performances. Transistors show a normally-OFF behavior with a high I_ON/I_OFF (~10⁹) ratio and a significantly small gate leakage current (10⁻¹¹ A/mm). Thanks to an improved resistance partitioning method, the resistances of the trench bottom and trench channel were extracted accurately by taking into account different charging conditions. This methodology enabled an estimation of the effective channel and bottom mobility of 11.1 cm²/V·s and 15.1 cm²/V·s, respectively.

This work presents a comprehensive study of GaN-on-Si pseudo-vertical MOSFETs focusing on single-trench and multi-trench designs. Thanks to a gate-first process flow based on an Al₂O₃/TiN MOS stack, both fabricated devices exhibit promising transistor behavior, with steady normally OFF operation, very low gate leakage current, and good switching performance. Following the extraction of a low effective channel mobility, the frequency dependence of gate-to-source C–V characteristics is studied. In addition, using TCAD Sentaurus Synopsys simulations, the impact of positive fixed charge and donor-type defects at the p-GaN/dielectric interface is investigated, together with the frequency dependency. Finally, by comparing experimental and simulated results, a mechanism is proposed linking the observed threshold voltage shift to the presence of sharp trench-bottom micro-trenching. This mechanism may further explain the origin of the additional C–V hump observed at high frequencies, which could arise from charge trapping at the p-GaN/dielectric interface or from charge inversion in the p-GaN region.

In this article, the impact of device architecture on threshold voltage VTH instabilities during OFF state operation under a high drain voltage stress on GaN-on-Si MOSc HEMTs is thoroughly investigated. Measurement-stress–measurement high-voltage bias temperature instability (HVBTI) technique using ultrafast VGS ramp was used in this study. This measurement technique was carried out on various gate length ( ${L}_{G}$ ), ohmic length (LOHM), and field plate (FP) length. HVBTI transients performed at different ${L}_{G}$ highlight that increasing the gate length induces a better electrostatic control under the gate via a gate shielding. TCAD simulations support the claim that the relaxation peak is linked to the charge redistribution of ionized ${C}_{N}$ (-) traps under the gate. This charge redistribution during the relaxation phase is enhanced using a larger ohmic contact area. The electric field at gate and source FP corners has a strong impact on ionized ${C}_{N}$ acceptor traps located in the GaN:C layer close to the gate and consequently on positive VTH degradation observed for short stress duration. Substrate biasing and TCAD simulations suggest that the ${C}_{N}$ traps’ deionization and trapping in the volume of the gate oxide is related to the presence of free holes in the GaN:C layer.

Today, wide bandgap (WBG) GaN semiconductors are considered the future, allowing the improvement of power transistors. The main advantage of GaN is the presence of two-dimensional electron gas (2Deg) typically used as a conduction layer in normally-on and normally-off transistors. Concerning the normally-off family, several solutions are proposed. Among these, one of the most promising is the MIS-Gate technology that features a gate recess architecture allowing the semiconductor to physically cut off the 2Deg and drastically decrease gate–source leakage currents. The Vth relaxation characteristic, after voltage stress, has been investigated. It has been shown that the main impact is due to charges close to the gate dielectric/GaN interface, precisely dwelling within the dielectric or the GaN epitaxy. This work provides an analytical model of the Vth evolution of these MIS-GATE (metal insulator semiconductor gate) transistors fabricated on GaN-silicon substrate. This model allows the extraction of different trap energy levels from a temporary threshold voltage (Vth) shift after 650 V stress. Based on this method, it is possible to identify up to four different trap energy levels. By comparing state of the art methods, we show that these obtained energy levels are well correlated with either magnesium and carbon impurity or Ga and/or N vacancy sites in the GaN epitaxy.