In this paper, a sensor using modified Split Ring Resonators (SRRs) is designed, simulated, fabricated, and used for advanced investigation and precise measurements of the real part and imaginary part solid dielectrics’ permittivity. Adding vertical strips tightly coupled to the outer ring of the SRR leads to the appearance of two resonant frequencies at 1.24 GHz and 2.08 GHz. This modified geometry also assures an improved sensitivity. Using the full wave electromagnetic solver, both the unloaded and loaded sensors are investigated. The numerical simulations are used to develop a mathematical model based on a curve fitting tool for both resonant frequencies, allowing to obtain analytical relations for real and imaginary parts of permittivity as a function of the sample’s thickness and quality factor. The sensor is designed and fabricated on 1.6 mm thick FR-4 substrate. The measurements of different samples, such as transparent glass, acrylic glass, plexiglass, and Teflon, confirm that the modified SRR sensor is easy to implement and gives accurate results for all cases, with measurement errors smaller than 4.5%. In addition, the measurements highlight the importance of the second resonant frequency in the cases in which numerical limitations do not allow the usage of the first resonant frequency (1 mm thick sample).

Stencil printing is the most crucial process in reflow soldering for the mass assembly of electronic circuits. This paper investigates different machine learning-based methods to predict the essential process characteristics of stencil printing: the area, thickness, and volume of deposited solder paste. The training dataset was obtained experimentally by varying the printing speed (from 20 to 120 mm/s), the size (area ratio from 0.35 to 1.7) of stencil apertures, and the particle size (characterized by a log-normal distribution) in the solder paste. Various machine learning-based methods were assessed; ANFIS–adaptive neuro-fuzzy inference systems; ANN artificial neural networks (with different learning methods); boosted trees, regression trees, SVM–support vector machines. Each method was optimized and fine-tuned with hyperparameter optimization, and the overfitting phenomenon was also prevented with cross-validation. The regression tree was the best performing approach for modelling the stencil printing, while ANN with the Bayesian regularization learning method was only slightly worse. The presented methodology for fine-tuning, parameter optimization, and the comparison of different machine learning-based methods can easily be adapted to any application field in electronics manufacturing.

In mixed-signal integrated circuits, interference between digital noisy and sensitive analog/RF circuits is a challenging performance issue. The high cost of chip fabrication requires accurate simulation of the circuits’ performance versus signal and noise integrity. In this paper, a substrate crosstalk noise analysis flow is described and the characteristics of the substrate noise coupling mechanism are analyzed. The proposed noise integrity aware simulation flow properly estimates the substrate coupling effect and predicts the analog/RF victim circuit performance degradation due to noise coupling mechanisms. The methodology is implemented seamlessly in the current standard virtuoso-based design suite and is used in parallel with any commercial design tool, compatible with the standard analog/RF simulation process. The efficiency of the proposed methodology is validated by a full substrate crosstalk aware system on chip vehicle, designed in an RFCMOS 65 nm process. Silicon substrate, interconnect parasitics and package parasitics are efficiently modeled so as to enable the substrate noise simulation. A substrate crosstalk system on chip vehicle is designed in a 65 nm RFCMOS. The crosstalk noise victim is a 5 GHz CMOS LNA and the noise aggressor is a 90 kGates digital logic. It is demonstrated that by applying the proposed methodology, substrate crosstalk performance degradation can be efficiently captured. The LNA carrier degradation and the spectrum distortion re efficiently simulated by identifying all of the noise spurs propagating through the common silicon substrate from the digital logic to the custom low noise amplifier noise victim. The respective inter-modulation spurs are also captured.

The paper intents to present the applied research performed by a few Romanian technological teams for an optimum implementation of SAC alloys in electronics industry, based on RoHS Directive, in order to investigate the behavior of SAC solder alloys in electronic products. Because manufacturers will need to ensure that their products comply with the requirements of European Regulations by July 2006 and designers are forced to change their strategy to accommodate lead-free soldering and not only, the paper shall emphasize the work on understanding and implementing SAC alloys, trying to underline advantages and disadvantages during the manufacturing flow. These new materials must be correctly modeled for their electrical characteristics when designers are involved in signal integrity analysis issues. Special component placement rules and new configurations of various structures/masks have to be designed for a good compliance between PCB layout design and manufacturing process. The main goal of the paper is to find and promote new methods for reducing to zero all unknown factors which can affect the assembling and manufacturing process of electronic products.

The paper presents the applied research performed in the frame of RESPLATEPE Romanian CEEX national project destined to implementation of ecological technologies in electronics industry, based on based on RoHS and WEEE directives [3]. The work represents a multi-criteria approach in electronics packaging and emphasizes the activity of eight research partners involved in various phases of electronic manufacturing process. Under work are activities regarding electrical, rheological, climatic, and mechanical testing of experimental ecological modules and structures (the relative humidity controller presented in this contribution being one example) developed in the first stage. After them, the team will perform investigations of signals parameters, environmental factors and interconnection technologies influences on ecological electronic modules developed or destined for future development.