The matrix converter (MC) presents a promising topology that needs to overcome certain barriers (complexity of the modulation and control techniques, protection systems, etc.) in order to gain a foothold in the industry. Traditionally, the MC has been controlled by means of a DSP, together with a field-programmable gate array (FPGA). The sole aim of the latter is to perform the safe commutation of the converter. This involves a waste of resources, as the excellent features of the FPGA are infrautilized by the control system. This paper deals with the implementation of the double-sided space vector modulation (DS SVM), commutation, reference-frame changes, and protection of the MC through a series of hardware blocks (cores) integrally implemented in an FPGA. The designed cores are technology-independent descriptions, which means that the developed design can be used in the FPGAs of any manufacturer. Moreover, the proposed design, which has been validated experimentally, has obviated the need to use a DSP. Likewise, given that all the processing capabilities have been integrated in a single chip, it can be said that an FPGA-based system on a programmable chip (SoPC) has been designed. Due to the computational capacity of the developed cores, processing time is reduced to the order of nanoseconds. This allows a response in real time and very high modulation frequencies can be attained. Moreover, these cores operate independently, and simultaneously, therefore obviating the need for sequential control and its resulting latencies and leading to an increase in the safety of the MC.

Since the 1990s, the digitalization process has transformed the communication infrastructure within the electrical grid: proprietary infrastructures and protocols have been replaced by the IEC 61850 approach, which realizes interoperability among vendors. Furthermore, the latest networking solutions merge operational technologies (OTs) and informational technology (IT) traffics in the same media, such as time-sensitive networking (TSN)—standard, interoperable, deterministic, and Ethernet-based. It merges OT and IT worlds by defining three basic traffic types: scheduled, best-effort, and reserved traffic. However, TSN demands security against potential new cyberattacks, primarily, to protect real-time critical messages. Consequently, security in the smart grid has turned into a hot topic under regulation, standardization, and business. This survey collects vulnerabilities of the communication in the smart grid and reveals security mechanisms introduced by international electrotechnical commission (IEC) 62351-6 and how to apply them to time-sensitive networking.

A synchronized common sense of time is a key factor for many smart grid applications, such as the sample value process bus operation. The precision time protocol (PTP), as defined in IEEE 1588-2008 standard, is highly recommended for substation communication networks, because it enables synchronization accuracies in the nanoseconds range through conventional Ethernet-based networks. This paper explores the implementation of PTP functionalities on new Xilinx Zynq-7000 all programmable system-on-chip (SoC) device. Different PTP master and slave implementations have been analyzed taking benefit from the flexibility of the SoC all programmable devices. The explored features go from simple only-software versions aided by PTP support of Gigabit Media Access Controllers (GMACs)embedded in the processor section to high-accuracy solutions that include custom PTP hardware in the logic section of the device. For each configuration approach, two different experimental setups based on two Zynq commercial low-cost boards has been built, and the protocol performance has been evaluated by measuring time offset between the pulse per second output signals of the master and the synchronized slave. The results obtained from this analysis show excellent accuracy results, with time offsets in the range of 40 ns and standard deviations of less than 10 ns.