This paper presents a true‐time delay (TTD) using a commercial 0.13‐μm CMOS process for wideband phased‐array antennas without the beam squint. The proposed TTD consists of four wideband distributed gain amplifiers (WDGAs), a 7‐bit TTD circuit, and a 6‐bit digital step attenuator (DSA) circuit. The T‐type attenuator with a low‐pass filter and the WDGAs are implemented for a low insertion loss error between the reference and time‐delay states, and has a flat gain performance. The overall gain and return losses are >7 dB and >10 dB, respectively, at 2 GHz–18 GHz. The maximum time delay of 198 ps with a 1.56‐ps step and the maximum attenuation of 31.5 dB with a 0.5‐dB step are achieved at 2 GHz–18 GHz. The RMS time‐delay and amplitude errors are <3 ps and <1 dB, respectively, at 2 GHz–18 GHz. An output P1 dB of <−0.5 dBm is achieved at 2 GHz–18 GHz. The chip size is 3.3 × 1.6 mm², including pads, and the DC power consumption is 370 mW for a 3.3‐V supply voltage.

Presented is a compact X‐band bidirectional gain amplifier in 0.18 μ m CMOS, which eliminates two T/R switches in the conventional one. The gain of >14 dB and the in/output return losses of >8 dB are achieved at 8–14 GHz. The measured output P1dB is ~1 dBm at 10 GHz. The chip size is 0.62 × 0.60 mm ² , which is compact due to the removal of two T/R switches for the bidirectional operation. The DC power consumption is 54 mW at 1.8 V supply voltage. Nearly identical performance is achieved in the forward and reverse operations at X‐band. To the authors’ knowledge, this is the first demonstration of an X‐band CMOS bidirectional gain amplifier with the smallest size.

A fully integrated 24-GHz radar transceiver with one transmitter (TX) and two receivers (RXs) for compact frequency modulated continuous wave (FMCW) radar applications is here presented. The FMCW synthesizer was realized using a fractional-N phase-locked loop (PLL) and programmable chirp generator, which are completely integrated in the proposed transceiver. The measured output phase noise of the synthesizer is −80 dBc/Hz at 100 kHz offset. The TX consists of a three-bit bridged t-type attenuator for gain control, a two-stage drive amplifier (DA) and a one-stage power amplifier (PA). The TX chain provides an output power of 13 dBm while achieving <0.5 dB output power variation within the range of 24 to 24.25 GHz. The RX with a direct conversion I-Q structure is composed of a two-stage low noise amplifier (LNA), I-Q generator, mixer, transimpedance amplifier (TIA), a two-stage biquad band pass filter (BPF), and a differential-to-single (DTS) amplifier. The TIA and the BPF employ a DC offset cancellation (DCOC) circuit to suppress the strong reflection signal and TX-RX leakage. The RX chain exhibits an overall gain of 100 dB. The proposed radar transceiver is fabricated using a 65 nm CMOS technology. The transceiver consumes 220 mW from a 1 V supply voltage and has 4.84 mm² die size including all pads. The prototype FMCW radar is realized with the proposed transceiver and Yagi antenna to verify the radar functionality, such as the distance and angle of targets.

In this paper, a 4-bit digital step attenuator using 0.25 μm GaN HEMT technology for wideband radar systems is presented. A switched-path attenuator topology with resistive T-type attenuators and double-pole double-throw (DPDT) switches was used to achieve both low insertion loss and phase/amplitude error. The measured insertion loss of the reference state is 2.8–8.3 dB at DC-12 GHz. The input and output return loss are less than 12 dB at DC-12 GHz. An attenuation coverage of 30 dB with a least significant bit of 2 dB was achieved at DC-12 GHz. A root mean square (RMS) amplitude error of 1 dB and a phase error of 8.5° were achieved, respectively. The attenuator chip size is 2.45 mm × 1.75 mm including pads. To the best of the authors’ knowledge, this is the first demonstration of a GaN-based digital step attenuator.