This article presents a 24-GHz highly integrated phased array radar transceiver with four transmitters (TXs) and four receivers (RXs). To realize a wide field of view (FoV) and more efficiently reject the clutters, an automatic beam steering mode is realized. A beam scanning generator (BSG) and a frequency sweep generator (FSG) are proposed to steer the beam for each frequency-modulated continuous wave (FMCW) waveform sequence. The shape of the FMCW waveform, the number of beams, and the steering angles of beams can be reconfigured by initially setting the FSG and BSG. The TXs achieve an output power of 10.6 dBm and beam steering covering angles up to $\pm$ 50 $^{\circ}$ through a three-stage power amplifier (PA), a 6-bit phase shifter, and a 4-bit attenuator. The RXs achieve a noise figure (NF) of 13.5 dB and an overall gain of 105 dB. In the RXs, a two-stage low-noise amplifier (LNA) employs a low-k transformer for flat band gain. A range-compensation filter with a total 40-dB slope is realized using a trans-impedance amplifier (TIA) with DC offset cancellation (DCOC) and first-stage biquad bandpass filter (BPF). The proposed transceiver was fabricated using 65-nm CMOS with an area of 3 $\times$ 2.8 mm $^{2}$ .

A compact and highly efficient 24 GHz circularly polarized (CP) short range radar (SRR) module is proposed. The proposed SRR is configured by highly integrated right-hand CP (RHCP) transmit (Tx) and left-hand CP (LHCP) receive (Rx) antenna arrays and a single 4-Tx and 4-Rx CMOS radar IC. The Tx RHCP and Rx LHCP antenna elements are coplanarly and concentrically arranged to form a 2 × 2 configuration for each Tx and Rx. The concentric integration can effectively increase the area efficiency while maintaining a high Tx-to-Rx isolation due to the opposite CP. Further, the radar IC is fabricated with TSMC 65 nm process and directly mounted on the back of the complete module. Each Tx and Rx channels of the IC are connected to each Tx and Rx array elements through multilayered feed network and bonding wires. Then, the SRR is operated as one Tx with 1 × 4 array and four Rx with individual antennas. Lastly, the complete CP SRR module is successfully verified at 24 GHz with a detection range from 1 m to 20 m.

This article presents a 54–64-GHz CMOS transce-iver with four transmitters (4TXs) and four receivers (4RXs). This transceiver is able to generate continuous and single 10-GHz bandwidth chirp signals for frequency-modulated continuous wave (FMCW) radar. Dual-supply phase-locked loop (PLL), low-noise amplifier (LNA) with low-coupling factor transformer, and four-stage power amplifier (PA) with capacitive neutralization technique are designed to realize a 10-GHz bandwidth chirp. The voltage-controlled oscillator (VCO) operation range is from 26.9 to 32.54 GHz. The VCO phase noise is $-$ 93 dBc/Hz at a 1-MHz offset frequency from a 30-GHz carrier frequency. The averaged in-band phase noise of the PLL in operating frequency band is $-$ 67.4 dBc/Hz at 100 kHz offset frequency. The TXs, including 6-bit phase shifters, achieve a 9.63-dBm saturated output power and OP 1 dB of 6.75 dBm for each channel. The LNA achieves a return loss of less than 6.4 dB over the 54–64 GHz operating range. The RX overall gain, including the integrated analog baseband (ABB) with two-stage bi-quad bandpass filters (BPFs) is 80 dB, and noise figure (NF) is 11.6 dB. The proposed transceiver consumes 731.3 mA when operating all channels. This chip occupies 3 $\times$ 3.4 mm $^{{2}}$ and was fabricated in 65-nm CMOS technology.

A fully integrated 24-GHz radar transceiver with one transmitter (TX) and two receivers (RXs) for compact frequency modulated continuous wave (FMCW) radar applications is here presented. The FMCW synthesizer was realized using a fractional-N phase-locked loop (PLL) and programmable chirp generator, which are completely integrated in the proposed transceiver. The measured output phase noise of the synthesizer is −80 dBc/Hz at 100 kHz offset. The TX consists of a three-bit bridged t-type attenuator for gain control, a two-stage drive amplifier (DA) and a one-stage power amplifier (PA). The TX chain provides an output power of 13 dBm while achieving <0.5 dB output power variation within the range of 24 to 24.25 GHz. The RX with a direct conversion I-Q structure is composed of a two-stage low noise amplifier (LNA), I-Q generator, mixer, transimpedance amplifier (TIA), a two-stage biquad band pass filter (BPF), and a differential-to-single (DTS) amplifier. The TIA and the BPF employ a DC offset cancellation (DCOC) circuit to suppress the strong reflection signal and TX-RX leakage. The RX chain exhibits an overall gain of 100 dB. The proposed radar transceiver is fabricated using a 65 nm CMOS technology. The transceiver consumes 220 mW from a 1 V supply voltage and has 4.84 mm² die size including all pads. The prototype FMCW radar is realized with the proposed transceiver and Yagi antenna to verify the radar functionality, such as the distance and angle of targets.

This article presents a fractional- $N$ subsampling PLL (FN-SSPLL) with a phase rotation (PR) technique. The proposed PR-based FN-SSPLL has high output frequency resolution, low phase noise, and low rms jitter. In addition, it obtains an output frequency of fractional times by dithering the phase of the signal fed back into the voltage-controlled oscillator (VCO) to increase the resolution of the output frequency by using sigma-delta modulator (SDM) on the phase-locked loop (PLL). By adopting a subsampling structure, the proposed FN-SSPLL can improve in-band phase noise by $N^{2}$ compared to standard PLLs, and the PR technique can attenuate SDM noise to improve out-of-band phase noise. The proposed PR-based FN-SSPLL was fabricated in a TSMC 65-nm RF CMOS process. The operating frequency range is 27.2–31.2 GHz and the frequency resolution is 24 Hz. Moreover, the reference frequency is 100 MHz and the phase noise is $-$ 104.67 dBc/Hz at 400-kHz offset frequency when the carrier frequency is 29.1 GHz. Finally, the measured rms jitter from 1 kHz to 10 MHz is 92 fs, the total power consumption is 23 mW, the supply voltage is 1 V, and the FoM $_j$ is $-$ 247.1 dB.

This paper proposes a new structure of 24-GHz class-C voltage-controlled oscillator (VCO) using an auto-adaptive bias technique. The VCO in this paper uses a digitally controlled circuit to eliminate the possibility of start-up failure that a class-C structure can have and has low phase noise and a wide frequency range. To expand the frequency tuning range, a 3-bit cap-bank is used and a triple-coupled transformer is used as the core inductor. The proposed class-C VCO implements a 65-nm RF CMOS process. It has a phase noise performance of −105 dBc/Hz or less at 1-MHz offset frequency and the output frequency range is from 22.8 GHz to 27.3 GHz, which consumes 8.3–10.6 mW of power. The figure-of-merit with tuning range (FoM_T) of this design reached 191.1 dBc/Hz.