This paper presents a compact and power efficient one-chip optical phased array (OPA) transmitter (TX) for optical wireless communication (OWC). A traveling-wave-electrode Mach-Zehnder modulator (TWE-MZM) and mm-Wave driver, which would traditionally be implemented by bulky off-the-shelf components, are monolithically integrated with a silicon-based 1×64 OPA onto a single chip, reducing an active area of the entire system down to 6.4 mm ² . Moreover, a co-design and integration of TWE-MZM and mm-Wave driver largely minimizes the parasitics and mismatches of an interface between the TWE and mm-Wave driver. The 64-element optical antenna achieves beam divergence of 0.77˚ and 4.23˚ over transversal and longitudinal direction, respectively. The two-sided beam-steering angles of the array antenna in transversal and longitudinal direction are ±14.3˚ and 6.1˚, respectively, while the side-lobe suppression ratio is 7.81 dB. The co-integrated TWE-MZM and driver support a measured data rate up to 15 Gbps and consume 210 mW. To the best of our knowledge, our proposed electronic-photonic integrated circuit is the first OWC-application OPA TX, which monolithically integrates TWE-MZM, CMOS driver, and OPA all in one-chip.

This paper presents a 137-GHz bandwidth highlinearity CMOS distributed amplifier (DA) for ultra-wide bandwidth power amplification applications. Utilizing intrastack coupling and input-output transmission lines (TLs), the proposed DA achieves ultra-wide bandwidth and improved linearity. Folding the input and output TLs enables efficient transformer implementation without the need for additional large areas. Furthermore, the frequency-dependent coupling between the input and output TLs increases bandwidth up to 137 GHz. Each common source (CS) stage is capacitively coupled to the input TLs, allowing for different mode operations and enhancing linearity. The proposed CMOS DA boasts the widest bandwidth of 137-GHz among reported CMOS DAs, along with 16.5/15.2 dBm peak $\mathrm{P}_{\mathrm{s}\mathrm{a}\mathrm{t}}/$PidB and 15.1% peak PAE at 26 GHz. The proposed CMOS DA also achieves 505.9 GHz, $\mathrm{P}_{\mathrm{s}\mathrm{a}\mathrm{t}}\times \mathrm{B}\mathrm{W}\times \mathrm{P}\mathrm{A}\mathrm{E}/\mathrm{P}_{\mathrm{D}\mathrm{C}}$ figure-of-merit (FoM). To the best of our knowledge, our proposed CMOS DA achieves the highest FoM.

A 28 GHz fully differential eight-channel beamforming IC (BFIC) with multimode operations is implemented in 65 nm CMOS technology for use in phased array transceivers. The BFIC has an adjustable gain and phase control on each channel to achieve fine beam steering and beam pattern. The BFIC has eight differential beamforming channels each consisting of the two-stage bi-directional amplifier with a precise gain control circuit, a six-bit phase shifter, a three-bit digital step attenuator, and a tuning bit for amplitude and phase variation compensation. The Tx and Rx mode overall gains of the differential eight-channel BFIC are around 11 dB and 9 dB, respectively, at 27.0–29.5 GHz. The return losses of the Tx mode and Rx mode are >10 dB at 27.0–29.5 GHz. The maximum phase of 354° with a phase resolution of 5.6° and the maximum attenuation of 31 dB, including the gain control bits with an attenuation resolution of 1 dB, is achieved at 27.0–29.5 GHz. The root mean square (RMS) phase and amplitude errors are <3.2° and <0.6 dB at 27.0–29.5 GHz, respectively. The chip size is 3.0 × 3.5 mm², including pads, and Tx mode current consumption is 580 mA at 2.5 V supply voltage.