DDR4 die are commonly packaged in Ball Grid Array packages. The package solder balls develop fractures due to difference in the thermal co-efficient of expansion of the package and printed circuit board. The intermittent behavior of the fracture is due to the momentarily opening of the solder joint due to vibration or the warpage of the package and the printed circuit board. This intermittent behavior can result in no fault found phenomenon in memory systems. DDR4 response in the presence of an intermittent fracture depends on the location of defect. The defect can occur in clock, address or data channel. A test fixture is used to show the AC coupling nature of fracture in ball grid array package solder ball. The intermittent change in the height of fracture is analyzed using 3-D electromagnetic model of the solder ball using high frequency structure simulator (HFSS) software. HFSS model of the fractured solder ball is used along with DDR4 channel topology to compare the sensitivity of clock, address and data channel response to intermittent fracture. It is shown that the data channel is most sensitive to intermittent fracture. DDR4 data mask violation occurs for even a small fracture height of 0.1 μm. For clock channel, the eye degrades or becomes smaller as the fracture height increases from 0.1 μm to 3 μm. But even for 3 μm fracture height, clock eye diagram remains within DDR4 clock +/- 110 mV specification. For address channel the eye degrades or becomes smaller when the height of fracture increases from 0.1 μm to 3 μm. For fracture height of 3 μm, DDR4 address +/- 65 mV input specification violation occurs. Address channel is more sensitive to intermittent fracture as compared to clock channel. The analysis shows that there is always intermittent error in data channel due to intermittent fracture and there are more intermittent errors in address channel compared to clock channel.

This paper shows that an intermittent AC coupling defect occurring in a DDR4 data channel will cause more intermittent errors in DDR4, compared to such defect in DDR3. The intermittent AC coupling defect occurs due to intermittent fracture in DDR4 package solder ball. The defect causes DC offset in DDR4, which shifts the data signal or data eye and results in DDR4 data channel failure. The DC offset occurs due to the asymmetric nature of pseudo open drain termination scheme. DDR4 data channel response is compared with DDR3 channel. It is shown that pseudo random binary sequence (PRBS) pattern will always cause failure for DDR4, but PRBS will only cause failure in DDR3 if the sequence of consecutive 0's or 1's in PRBS pattern is long enough to cause threshold violation. As a result there will be more intermittent errors in DDR4 compared to DDR3. The defect due to fracture in solder ball is modelled by an AC coupling capacitor. A 1nF AC coupling capacitor corresponding to a solder ball fracture of height about 1nm is used to show the difference between DDR4 and DDR3 response.

This paper analyzes intermittent partial connection defect in Double data rate 4 (DDR4) memory data channel. DDR4 ball grid array package develops partial connection defect during device operation. Electrical model of defect is presented and Ansys software is used to extract resistance, inductance and capacitance change due to defect radius and defect height variation. Ansys 3-D electromagnetic field solver simulation is done to extract S-parameters of a pair of solder balls having intermittent partial connection defect. It is shown that there is noticeable signal degradation when defect height is above 0.1 um and radius is below 0.1 um values and this will result in intermittent errors. AC coupling behavior appears at small defect radius and 3 dB frequency changes with defect height and radius change. DDR4 data channel architecture is examined to show asymmetric behavior for logic “1” and logic “0”. Data channel response is analyzed in presence of partial connection defect and data eye channel loss and margin loss are used to characterize signal degradation. The area of partial connection is varied to observe the channel response change. As defect height increases, the radius at which DDR4 data specification violation occurs decreases. Data rate is varied to show channel loss increase for higher data rates. Eye margin is calculated to show decrease in low eye margin with data rate increase. DDR4 data channel asymmetric response causes logic “0” bit error rate to increase, whereas logic “1” bit error rate doesn’t change. This behavior can be used as a diagnostic symptom for intermittent partial connection defect detection.

This paper measures bit error rate degradation in DDR4 due to crack in fine pitch ball grid array (FBGA) package solder ball. Thermal coefficient mismatch between the package and printed circuit board material causes cracks to occur in solder balls. These cracks change the electrical model of the solder ball and introduce parallel capacitance in the electrical model. The capacitance causes higher frequency attenuation and closes the data eye. As the data rate of the DDR4 increases there are more data eye closures. The data eye closure causes bit error rate (BER) degradation as the timing margin and voltage margin decreases. This degradation reduces the reliability of the system and causes more intermittent errors. DDR4 data line is loaded with a parallel capacitive element to mimic a crack in solder ball. The measured data eye shows a decrease in eye width. Bathtub plots are created for comparison of cracked solder ball and intact solder ball. The bathtub plots show the BER degradation due to crack in solder ball.

Intermittent faults in electronic systems can cause catastrophic failures in mission-critical applications. However, because of the dynamic nature of intermittent faults, most of the errors disappear before they can be analyzed, complicating the identification and resolution of their root cause. In this study, we perform in-situ analysis of intermittent wire-bond defects observed in a complementary metal-oxide semiconductor buffer, to investigate their root cause. The waveform distortions representing various stages of an intermittent wire-bond defect are successfully captured by applying a liquid-nitrogen thermal shock that induces crack propagation because of the mismatched coefficients of thermal expansion. Simulation program with integrated circuit emphasis software is utilized for waveform analysis, and the propagation of nanoscale cracks is analyzed geometrically using a high-frequency structure simulator. Resistance levels ranging from several hundreds of ohms to kilo ohms and crack-induced capacitances up to 10 pF are observed, with the DC resistance contributing significantly to system errors. Moreover, we demonstrate electrical recovery through crack closures resulting from the thermal shock. The combination of crack propagation and closure is determined to be the root cause of intermittent failures. The analysis of wire-bond–defect characteristics, buffer architecture, and measured wire-bond–defect waveforms can help determine the location of the defect. Our results provide new insights into the propagation and recovery mechanisms of wire-bond cracks.