Power hardware-in-the-loop (PHIL) technology allows for the testing of physical equipment in a real-time simulation environment. An important role is attributed to the power interface. This power interface connects a power system model, which is implemented on a digital computer, to physical hardware under test, such as a power electronic converter. Several hardware-in-the loop (HIL) test setups with distinct power interfaces are proposed and compared. Based on detailed modeling of the different interfaces, system analysis is performed for each HIL test setup with respect to overall stability and accuracy. To verify stability for PHIL simulation systems, transfer function representations of the entire PHIL simulation processes are developed, and all involved time delays are quantified. The Nyquist stability criterion is applied to analyze all considered interfacing methods to enhance PHIL simulation stability, and the accuracy is evaluated. Moreover, experimental test results are given to demonstrate both the applicability and the functioning of the proposed interfacing methods. A particular focus is laid on the interfacing of physical power electronic inverters tested as part of a network in a PHIL real-time simulation.

Power hardware-in-the-loop (PHIL) technology allows for the testing of physical equipment including power electronic converters in a simulation environment that closely mirrors the reality of the electric power grid. A challenge involved in PHIL systems is the design of the interface between digital network model and physical equipment as this has a significant influence on stability of the real-time simulation. While a small time step supports stability and accuracy, its lower limit is given by the real-time constraint. The proposed multi-rate partitioning (MRP) interface addresses this issue by using a rather small time step at the hardware-software interconnection and then employing a staged adaptation of the time step within the digital model in accordance with the real-time constraint. Thus, multiple rates are used. The Nyquist stability criterion confirms enhanced stability and bandwidth by the MRP compared with single-rate (SR) counterparts. Moreover, a PHIL test of two parallel photovoltaic converters feeding a low-voltage network reveals different behaviors depending on the interface. Using the MRP, the waveforms more closely track the real-world curves of active and reactive power with the relative accuracy increasing with the speed of the transients. Informed decision making regarding the integration of renewables in the grid is so supported.

Investigations of the dynamic behaviour of power electronic components integrated into electric networks require suitable and established simulation methodologies. Real-time simulation represents a frequently applied methodology for analyzing the steady-state and transient behavior of electric power systems. This work introduces a guideline on how to model power electronics converters in digital real time simulators, taking into account the trade-off between model accuracy and the required computation time. Based on this concept, possible execution approaches with respect to the usage of central processing unit and field-programmable gate array components are highlighted. Simulation test scenario, such as primary frequency regulation and low voltage ride through, have been performed and accuracy indices are discussed for each implemented real-time model and each test scenario, respectively. Finally, a run-time analysis of presented real-time setups is given and real-time simulation results are compared. This manuscript demonstrates important differences in real-time simulation modelling, providing useful guidelines for the decision making of power engineers.

Power hardware-in-the-loop (PHIL) simulation leverages the advanced real-time emulation based technique to carry out in-depth investigations on novel real-world power components. Power amplifiers, sensors, and signal conversion units based power interfaces (PI) incorporate physical hardware systems and real-time simulation platforms into PHIL setups. However, the employment of any interfacing technique inevitably introduces disturbances such as sensor noise, switching harmonics, or quantization noise to PHIL systems. To facilitate quantitatively analyzing and assessing the impact of external disturbances on PHIL simulation systems, a framework for sensitivity analysis of PHIL setups has been developed in this paper. Detailed modelling principles related to the sensitivity analysis of PHIL systems and the inherent relationship between sensitivity transfer functions and stability criteria are elaborated along with theoretical and experimental validation. Based on this concept, accuracy assessment methods are employed in this framework to quantify generic sensitivity criteria. Moreover, physical passive load and converter-based PHIL setups are applied and experimental results are presented to characterize and demonstrate the applicability of the proposed framework.

Testing inverter-based resources (IBRs) is of utmost importance. This paper proposes a novel power hardware-in-the-loop (PHIL) interface control (PHIL-IC) employing a reinforcement-learning approach based on adaptive dynamic programming (ADP, also known as approximate dynamic programming) to enhance the PHIL-simulation-based testing of IBRs by virtue of an ADP-based method. It deploys output feedback control because of “unavailable” or “uncertain” dynamics of the entire systems (states and disturbances) linked to IBRs, power amplifiers, all the components associated with the PHIL-simulation-based testing, and their delays; it optimally designs PHIL-IC while considering all uncertainties and unavailable information about all the systems involved. To this end, the proposed ADP-based PHIL-IC utilizes a new hybrid iteration (HI) method, which differs from the traditional ADP strategies; compared with the policy iteration method, the HI algorithm does not require prior knowledge of an admissible control policy. Moreover, with a quadratic rate of convergence, the proposed HI method converges much faster than the value iteration method. Therefore, the proposed HI method saves significant learning time and iterations compared to the value iteration method. Comparing the results of the PHIL-simulation-based testing utilizing the proposed method with those of the proportional-resonant controller (as the conventional PHIL-IC) and the robust PHIL-IC based on $\mu$ synthesis (as the current state-of-the-art PHIL-IC) reveals the effectiveness and practicality of the proposed method. Those comparative results are generated by the ideal transformer model (also known as voltage-type interface) commonly used in the PHIL-simulation-based testing and practical cases of the Thévenin equivalent impedance (resistive, resistive-inductive, and inductive ones) of the model of interest associated with the power networks.

A novel power hardware-in-the-loop interface algorithm, the virtual shifting impedance, is developed, validated, and demonstrated in this article. Building on existing interface algorithms, this method involves shifting a part of the software impedance to the hardware side to improve the stability and accuracy of power hardware-in-the-loop setups. However, compared to existing approaches, this impedance shifting is realized by modifying the command signals of the power amplifier controller, thus avoiding the requirement for hardware passive components. The mathematical derivation of the virtual shifting impedance interface algorithm is realized step by step, while its stability and accuracy properties are thoroughly examined. Finally, the applicability of the proposed method is verified through power hardware-in-the-loop simulation results.