The stability and accuracy of power hardware-in-the-loop (PHIL) setups are sensitive to and deteriorated by the dynamics and nonideal characteristics of their power interfaces, such as time delay, noise perturbation, and signal distortion. In this article, a compensation scheme comprising a Smith predictor compensator is proposed to mitigate the impact of time delay on PHIL stability. Furthermore, an online system impedance identification technique is leveraged to enhance the robustness of the compensator and facilitate the compensation scheme with adaptivity to system impedance variation. Analytical assessment, simulation results, and PHIL experimental results are presented to verify the proposed compensation scheme. This scheme enables robust and stable testing of novel power technologies under varying impedance ratios representative of the complex scenarios emerging within the power sector.

Power hardware-in-the-loop (PHIL) simulation leverages the advanced real-time emulation based technique to carry out in-depth investigations on novel real-world power components. Power amplifiers, sensors, and signal conversion units based power interfaces (PI) incorporate physical hardware systems and real-time simulation platforms into PHIL setups. However, the employment of any interfacing technique inevitably introduces disturbances such as sensor noise, switching harmonics, or quantization noise to PHIL systems. To facilitate quantitatively analyzing and assessing the impact of external disturbances on PHIL simulation systems, a framework for sensitivity analysis of PHIL setups has been developed in this paper. Detailed modelling principles related to the sensitivity analysis of PHIL systems and the inherent relationship between sensitivity transfer functions and stability criteria are elaborated along with theoretical and experimental validation. Based on this concept, accuracy assessment methods are employed in this framework to quantify generic sensitivity criteria. Moreover, physical passive load and converter-based PHIL setups are applied and experimental results are presented to characterize and demonstrate the applicability of the proposed framework.

Power systems worldwide are experiencing rapid evolvements with a massive increase of renewable generation in order to meet the ambitious decarbonization targets. A significant amount of renewable generation is from Distributed Energy Resources (DERs), upon which the system operators often have limited visibility. This can bring significant challenges as the increasing DERs’ can lead to network constraints being violated, presenting critical risks for network security. Enhancing the visibility of DERs can be achieved via the provision of communication links, but this can be costly, particularly for real time applications. Digital Twin (DT) is an emerging technology that is considered as a promising solution for enhancing the visibility of a physical system, where only a limited set of data is required to be transmitted with the rest data of interest can be estimated via the DT. The development and demonstration of DTs requires realistic testing and validation enviorment in order to accelerate its adoption in the industry. This paper presents a real time simulation and hardware-in-the-loop (HiL) testing platform, specifically designed for prototyping, demonstrating and testing DTs of DERs. Within the proposed platform, a software-based communication emulator is developed, which allows the investigation of the impact of communication latency and jitter on the performance of DTs of the DERs. Case studies are presented to demonstrate the application of the developed DT prototyping process and testing platform to enable frequency control using the DTs, which provide valuable learnings and tools for enabling future DTs-based solutions.

A novel power hardware-in-the-loop interface algorithm, the virtual shifting impedance, is developed, validated, and demonstrated in this article. Building on existing interface algorithms, this method involves shifting a part of the software impedance to the hardware side to improve the stability and accuracy of power hardware-in-the-loop setups. However, compared to existing approaches, this impedance shifting is realized by modifying the command signals of the power amplifier controller, thus avoiding the requirement for hardware passive components. The mathematical derivation of the virtual shifting impedance interface algorithm is realized step by step, while its stability and accuracy properties are thoroughly examined. Finally, the applicability of the proposed method is verified through power hardware-in-the-loop simulation results.

Parallel operation of power converters in islanded DC microgrids exhibits significant trade-off in voltage regulation and current sharing with conventional droop control. The converters exhibit inaccuracies in proportionate sharing of current when subject to heavy and transient loading while sharing a common bus. Moreover, the inaccuracies further persist due to unmodeled dynamics, parametric uncertainties, disturbance in the system and communication reliability. Therefore, the resilient parallel operation of power converters in DC microgrids requires a robust and fast control strategy that can mitigate the effect of disturbances and maintain regulated bus voltage with proportional current sharing amongst the power converters. Consequently, this work proposes a novel ANN driven droop control for a DC microgrid to enhance the transient response and mitigate disturbance in finite time. Two controllers based on adaptive droop strategy are proposed; the primary controller is a generalized Hebb's learning law-based PI integrated controller that can adjust the gains in real time for finite-time disturbance compensation in the networks and the secondary control regulates the bus voltage using fractional order sliding mode control. The effectiveness of the proposed method is evaluated by simulation and experiment and compared with the conventional and distributed droop control methods, proving its robust and adaptive performance for resilient DC microgrid applications.

This letter assesses the impact of phase locked-loop (PLL) cyberattacks on inverter-dominated microgrids considering the current limitation of the grid forming (GFM) and grid following (GFL) inverters. By reducing the PI gains of the PLL, an adversary can induce significant voltage sags by exploiting the dynamic coupling between the GFL’s synchronization loop and the GFM’s droop controller. The study demonstrates that preemptive tuning of lower droop gains in GFM inverters can mitigate the effects of such attacks. Leveraging this inherent cyber-resilience of inverter-dominated microgrids, an active decentralized droop adjustment mechanism is proposed. Power hardware-in-the-loop experiments validate the time-domain analysis and the effectiveness of the proposed mitigation strategy.