This paper presents a pulse width modulation strategy for the cancellation of common-mode (CM) voltage generated by three-phase back-to-back two-level inverters. This method theoretically provides complete elimination of the CM voltage by synchronizing all the commutations of one converter with commutations of the other one, so that the overall resulting CM voltage does not vary. The degrees of freedom of this strategy are studied and an experimental implementation is carried out on a 15-kW motor drive prototype to validate the method effectiveness. Taking into account deadtime compensation, measurements in time and frequency domains show that the CM voltage is strongly reduced and that more than 15 dB reduction is achieved in a wide frequency range.

High-frequency power converters need electromagnetic interferences filters using common and differential mode chokes with low parasitic capacitance to comply with the electromagnetic compatibility standards. This article proposes a modeling method of this capacitance and ways to minimize it. The studied components are ring core inductors with magnetic materials considered as perfect conductors or with high permittivity, such as nanocrystalline material and most Mn-Zn ferrite materials. In comparison to other work in the literature, the proposed approach takes into account the curvature of the turn, in addition to the coating of the core and the insulation layer of the wire. The hypotheses, used in this article to simplify the real geometry, are compatible with two-dimensional (2-D) approaches to compute the parasitic interturns and turn–core capacitances. These capacitances are evaluated thanks to the 2-D finite element method. The obtained model allows accurate evaluation of the effect of turn–core space on the parasitic capacitance, and enables to reduce its value with a limited impact on the volume of the magnetic component.

ElectroMagnetic Interferences (EMI) filters are broadly used in power electronic systems in order to respect EMC normative constraints, which considerably increase overall cost and volume mainly because of the common-mode inductor. In this paper, a new method to calculate the minimum volume of the common-mode inductor is proposed. It takes into account core saturation issues that may greatly impact inductor volume and filter performances. Consequently, it is shown that in some cases, increasing the inductance value up to the optimal value can significantly reduce the filter volume in addition to further enhancing filter attenuation. It is also shown that different near-optimal inductor geometrical parameters with different shape factors can be obtained, which provides an important degree of freedom to designers while introducing the filter in the energy conversion system.

The new power GaN transistors allow to increase the operating frequency of converters to megahertz range, thanks to their low switching time that is of a few nanoseconds or less. This permits to reduce the values and the volume of the passive components, and enhance the power density of power converters. However, inductors needed for energy storage still take a large volume in converters compared with the others components, because of their weak energy density. Further, high-frequency operation require low-losses magnetic materials. In this paper, a design method of PCB inductors is proposed. A flexible ferrite sheet is used to enhance the inductance value and ease the realization of custom-shape devices. The design method of the inductor is based on the optimization of the inductor volume taking into account thermal issues of the magnetic sheets. Also a simulation method is proposed to calculate the equivalent stray capacitance of the inductors. The proposed method provides a losses-volume trade-off that helps designers to optimize the inductor for their application.

In order to better predict the high-frequency switching operation of transistors in power converters, parasitic elements of these devices such as resistances, inductances, and capacitances must be accurately evaluated. This paper reports on the characterization of a gallium nitride (GaN) packaged power transistor using S-parameters in order to extract the device parasitics. Because the transistor is packaged, a calibration technique is carried out using specific test fixtures designed on FR4 printed circuit board (PCB) in order to get the S-parameters in the transistor plane from the measurement. The proposed method is suitable for a wide range of power devices. In this paper, it is applied to an enhancement-mode GaN high electron mobility transistor (HEMT). The impact of junction temperature on drain and source resistances is also evaluated. According to characterization results, equation-based modeling is proposed for the nonlinear parameters. The extracted parasitic elements are compared with reference values given by the device manufacturer.