Resistive Random Access Memories (RRAMs) are based on resistive switching (RS) operation and exhibit a set of technological features that make them ideal candidates for applications related to non-volatile memories, neuromorphic computing and hardware cryptography. For the full industrial development of these devices different simulation tools and compact models are needed in order to allow computer-aided design, both at the device and circuit levels. Most of the different RRAM models presented so far in the literature deal with temperature effects since the physical mechanisms behind RS are thermally activated; therefore, an exhaustive description of these effects is essential. As far as we know, no revision papers on thermal models have been published yet; and that is why we deal with this issue here. Using the heat equation as the starting point, we describe the details of its numerical solution for a conventional RRAM structure and, later on, present models of different complexity to integrate thermal effects in complete compact models that account for the kinetics of the chemical reactions behind resistive switching and the current calculation. In particular, we have accounted for different conductive filament geometries, operation regimes, filament lateral heat losses, the use of several temperatures to characterize each conductive filament, among other issues. A 3D numerical solution of the heat equation within a complete RRAM simulator was also taken into account. A general memristor model is also formulated accounting for temperature as one of the state variables to describe electron device operation. In addition, to widen the view from different perspectives, we deal with a thermal model contextualized within the quantum point contact formalism. In this manner, the temperature can be accounted for the description of quantum effects in the RRAM charge transport mechanisms. Finally, the thermometry of conducting filaments and the corresponding models considering different dielectric materials are tackled in depth.

The two main issues in the area of the Internet of Things are low-resource consumption and secure data transmission. Conjugating both is fairly hard on ensuring security, leading to great efforts in research. The standard cryptography methods currently proposed are based on simplifications of standard protocols, but are still demanding on resources. Chaotic encryption is a way to reduce this burden, while keeping an equivalent level of security. In this article, we propose, for the first time, a purely digital scheme for chaotic secure communications, able to be implemented in hardware or software without occupying most of the available resources. Next to the delivered analysis of the system, the experimental demonstration on both FPGA and ESP32 Arduino platforms of chaotic synchronization between transmitter and receiver, included examples of applied encrypted communication in the case of consecutive picture and text transmissions.

In this paper, we develop and test a piecewise model for the reset and set transitions of a bipolar ReRAM memristive device in the flux-charge space, instead of the usual voltage-current one. To do so, we consider the devices as memristors. The model used is very simple and provides accurate simulation results. It also allows the development of simple expressions for the conductance and power consumption, as well as the characterization of the ReRAM memristive device in voltage-current domain by using two points for any reset or set cycle. We consider the case of a ramp input signal with different slopes to obtain the model parameters, and we compare the predictions of our model with experimental results.

Memristors were first proposed in 1971 by Leon Chua. These devices are usually regarded as being one of the newest fundamental breakthrough for electronics. Their role in designing new electronic systems is expected to be an important, key-factor. As an example, they already come in many forms: PCA, ReRAM, etc., to mention a few. In any case, since actual memristors have only appeared quite recently, this technology has yet to be mature enough to provide with readily available, off-the-shelf components. This implies that developing and testing new concepts or design architectures based on memristors are performed mainly by the use of numerical simulation. In this paper, we discuss a powerful modeling framework that eases creating and implementing new memristor models, illustrating with some examples of use.

In this work, we present a compact memristor model for bipolar neuromorphic ReRAM devices. The proposed model focuses on a behavioural high level description of the device, and it reproduces some of the most important characteristics (i.e. conductance, energy dissipation), using the number of pulses as the input variable instead of any electrical. Its functionality is shown by using it to model the behavior of three different ReRAM devices that were fabricated and measured at the CNR-IMM, Agrate Brianza. Considering a train of identical pulses as an input voltage signal consisting of N pulses and where m is the pulse number. The conductance during depression or potentiation can be described.

The Hindmarsh–Rose model is one of the most used models to reproduce spiking behaviour in biological neurons. However, since it is defined as a system of three coupled differential equations, its implementation can be burdensome and impractical for a large number of elements. In this paper, we present a successful implementation of this model within a stochastic computing environment. The merits of the proposed approach are design simplicity, due to stochastic computing, and the ease of implementation. Simulation results demonstrated that the approximation achieved is equivalent to introducing a noise source into the original model, in order to reproduce the actual observed behaviour of the biological systems. A study for the level of noise introduced, according to the number of bits in the stochastic sequence, has been performed. Additionally, we demonstrate that such an approach, even though it is noisy, reproduces the behaviour of biological systems, which are intrinsically noisy. It is also demonstrated that using some 18–19 bits are enough to provide a speedup of x2 compared to biological systems, with a very small number of gates, thus paving the road for the in silico implementation of large neuron networks.