This brief presents a tutorial on topologies of piezoelectric energy harvesting circuits. The latest design technologies are systematically summarized. The topologies are classified according to the energy storage devices and the input excitation. The working principles and design strategies of different topologies are compared and analyzed. Considerations such as topology generation, loss analysis and optimization, system volume and energy efficiency are also discussed.

This article proposes a novel eight-phase self-bias-flip piezoelectric energy harvesting interface with charge recycling and reusing (SBFRR) and a switched-piezoelectric energy harvester (PEH) dc–dc (SPDC) converter. The proposed scheme innovatively utilizes the inherent capacitors ( $C_P$ ) of four PEHs as energy sources, flying capacitors, and flipping capacitors for time-sharing reuse to achieve both a high-voltage flipping and dc–dc conversion efficiency, while avoiding the use of extra energy reservoirs. The design is fully integrated and fabricated in standard 0.18- $\mu$ m CMOS. Measurement result demonstrates that the voltage flipping efficiency of up to 80% is achieved. Compared with the ideal full-bridge rectifier (FBR), the measured maximum output power improving rate (MOPIR) can be increased to 4.88 $\times$ . In addition, with the four $C_P$ serving as flying capacitors to achieve SPDC conversion for maximum power point track (MPPT), an MOPIR of $>$ 3.5 $\times$ can be maintained with a PEH input voltage from 0.78 to 4.9 V.

This brief presents a tutorial on multifaceted techniques for high efficiency piezoelectric energy harvesting. For the purpose of helping design piezoelectric energy harvesting system according to different application scenarios, we summarize and discuss the recent design trends and challenges. We divide the design focus into the following three categories, namely, (1) AC-DC rectifiers, (2) C_P compensation circuits, (3) maximum power point tracking (MPPT) circuits. The features, problems encountered, and suitable systems of various AC-DC rectifier topologies are introduced and compared. The important role of non-linear methods for piezoelectric energy harvesting is illustrated from the perspective of impedance matching. Energy extraction techniques and voltage flipping techniques based on inductors, capacitors, and hybrid structures are analyzed. MPPT techniques with different features and targets are discussed.

This article presents a 10 mV-startup-voltage thermoelectric energy harvesting system, assisted by a piezoelectric generator (PEG) as a cold starter. It exploits the fact that when a thermoelectric energy harvesting system is implemented in a place where kinetic energy is also present, the PEG starter can provide a clock signal to start the system. Thanks to the high output impedance of the PEG, the generated clock voltage can easily go over several hundreds of mV, which can be used to drive the boost converter to harvest thermoelectric energy even at an extremely low thermoelectric generator (TEG) voltage. The proposed system was fabricated in a 180-nm BCD process. The measurement results show that the TEG system can start up from the cold state with a TEG voltage as low as 10 mV while maintaining a 63.9% efficiency. The peak power conversion efficiency reaches 83.7% when the TEG voltage is 55 mV.

Multiple voltage conversion ratio (VCR) recursive switched-capacitor (SC) dc–dc converters, based on several basic 2:1 converters, are widely used for on-chip power supplies due to their flexible VCRs for higher energy efficiency. However, conventional multiple VCR SC converters usually have one or more 2:1 converters unused for some VCRs, which results in lower power density and chip area wastage. This article presents a new recursive dc–dc converter system, which can dynamically reconfigure the connection of all on-chip 2:1 converter cells so that the unused converters in the conventional designs can be reused in this new architecture for increasing the load-driving capacity, power density, and power efficiency. To validate the design, a 4-bit-input 15-ratio system was designed and fabricated in a 180-nm BCD process, which can support a maximum load current of $\text{0.71}\,\text{mA}$ and achieves a peak power efficiency of 93.1% with $105.3\,\mu \text{A/mm}^{2}$ chip power density from a 2-V input power supply. The measurement results show that the load-driving capacity can become 6.826×, 2.236×, and 2.175× larger than the conventional topology when the VCR is 1/2, 1/4, and 3/4, respectively. In addition, the power efficiency under these specific VCRs can also be improved considerably.

Synchronized rectifiers offer promising solutions for piezoelectric energy harvesting; however, achieving the promised energy extraction performance necessitates using either a bulky inductor or multiple large capacitors, which cannot be on-chip integrated and increase the system form factor. This article introduces a fully integrated sequenced synchronized switch harvesting on capacitors (3SHC) rectifier. The input piezoelectric transducer (PT) uses microelectromechanical system technology. The cantilever is equally split into multiple strongly coupled subcantilevers, with each cantilever treated as an individual PT connected to the proposed rectifier. The 3SHC rectifier cyclically operates multiple times to synchronously flip the voltage of each cantilever sequentially. With the proposed design, all the flying capacitors only need to match the capacitance of each subcantilever; hence, they can be fully integrated on-chip. The design is fabricated using standard 0.18 $\mu \text{m}$ CMOS technology. Measurement results show that the proposed 3SHC rectifier attains an 80% voltage flip efficiency and achieves a 730% power enhancement compared to a full-bridge rectifier.