Combined effects of electrical stress and neutron irradiation of the last generation of commercial discrete silicon carbide power MOSFETs are studied. The Single Event Burnout (SEB) sensitivity during neutron irradiation is analyzed for unstressed and electrically stressed devices. For surviving devices, a comprehensive study of the breakdown voltage degradation is performed by coupling electrical stress and irradiation effects. In addition, mutual influences between electrical stress and radiative constraints are investigated through TCAD modeling.

Functional verification schemes at a level different from component-level testing are emerging as a cost-effective tool for those space systems for which the risk associated with a lower level of assurance can be accepted. Despite the promising potential, system-level radiation testing can be applied to the functional verification of systems under restricted intrinsic boundaries. Most of them are related to the use of hadrons as opposed to heavy ions. Hadrons are preferred for the irradiation of any bulky system, in general, because of their deeper penetration capabilities. General guidelines about the test preparation and procedure for a high-level radiation test are provided to allow understanding which information can be extracted from these kinds of functional verification schemes in order to compare them with the reliability and availability requirements. The use of a general scaling factor for the observed high-level cross sections allows converting test cross sections into orbit rates.

The mechanisms responsible for neutron-induced single-event burnout (SEB) in commercial silicon carbide power MOSFETs under atmospheric-like neutron spectrum were investigated and analyzed. The combined effect of applied reverse gate voltage and drain voltage was evaluated. First, local analysis of the packaged device at the wafer level is performed to reveal the failure mechanism inside the semiconductor lattice. Second, based on gate stress testing of surviving devices and looking at the influence of reverse gate bias during irradiation, an enhanced failure sensitivity especially for drain voltage values close to the safe operating area was demonstrated. In addition to support this assumption, TCAD simulations with damage sites were performed in order to address physical mechanisms related to gate leakage degradation and SEB.

The effect of 53 MeV proton irradiation on the reliability of silicon carbide power MOSFETs was investigated. Post-irradiation gate voltage stress was applied and early failures in time-dependent dielectric breakdown (TDDB) test were observed for irradiated devices. The applied drain voltage during irradiation affects the degradation probability observed by TDDB tests. Proton-induced single event burnouts (SEB) were observed for devices which were biased close to their maximum rated voltage. The secondary particle production as a result of primary proton interaction with the device material was simulated with the Geant4-based toolkit.

Testing at system level is evaluated by measuring the sensitivity of point-of-load (PoL) converter parameters, submitted to total ionizing dose (TID) irradiations, at both system and component levels. Testing at system level shows that the complete system can be fully functional at the TID level more than two times higher than the qualification level obtained using a standard-based component-level approach. Analysis of the failure processes shows that the TID tolerance during testing at system level is increased due to internal compensation in the system. Finally, advantages and shortcomings of the testing at system level are discussed.

The effect of 20 MeV electron radiation on the lifetime of the silicon carbide power MOSFETs was investigated. Accelerated constant voltage stress (CVS) was applied on the pristine and irradiated devices and time-to-breakdown ( T _BD ) and charge-to-breakdown ( Q _BD ) of gate oxide were extracted and compared. The effect of electron radiation on the device lifetime reduction can be observed at lower stress gate-to-source voltage ( V _GS ) levels. The models of T _BD and Q _BD dependence on the initial gate current ( I _G0 ) are proposed which can be used to describe the device breakdown behaviour.