An ultrafast Active Quenching—Active Reset (AQAR) circuit is presented for the afterpulsing reduction in a Single Photon Avalanche Diode (SPAD). The proposed circuit is designed in a 28 nm Fully Depleted Silicon On Insulator (FD-SOI) CMOS technology. By exploiting the body biasing technique, the avalanche is detected very quickly and, consequently, is quenched very fast. The fast quenching decreases the avalanche charges, therefore resulting in the afterpulsing reduction. Both post-layout and experimental results are presented and are highly in accordance with each other. It is shown that the proposed AQAR circuit is able to detect the avalanche in less than 40 ps and reduce the avalanche charge and the afterpulsing up to 50%.

The usage of single-photon avalanche diode arrays is becoming increasingly common in various domains such as medical imaging, automotive vision systems, and optical communications. Nowadays, thanks to the development of microelectronics technologies, the SPAD arrays designed for these applications has been drastically well-facilitated, allowing for the manufacturing of large matrices. However, there are growing challenges for the design of readout circuits with the needs of reducing their energy consumption (linked to the usage cost) and data rate. Indeed, the design of the readout circuit for the SPAD array is generally based on synchronous logic; the latter requires synchronization that may increase the dead time of the SPADs and clock trees management that are known to increase power consumption. With these limitations, the long-neglected asynchronous (clockless) logic proved to be a better alternative because of its ability to operate without a clock. In this paper, we presented the design of a 16-to-1 fixed-priority tree arbiter readout circuit for a SPAD array based on asynchronous logic principles. The design of this circuit was explained in detail and supported by simulation results. The manufactured chip was tested, and the experimental results showed that it is possible to record up to 333 million events per second; no reading errors were detected during the data extraction test.

Conception d'un capteur de photon unique en technologie 28 nm FD-SOI CMOS: Les photodétecteurs à avalanche de photons uniques (SPAD) suscitent un intérêt croissant dans les applications de comptage de photons pour lesquels un taux de comptage élevé est nécessaire. Dans les pixels à SPAD conventionnels, un taux de comptage élevé est généralement source de bruit dit « afterpulsing ». Les circuits d’extinction active (AQ) sont une solution pour limiter cet effet au prix d’une consommation de surface supplémentaire réduisant ainsi la sensibilité du pixel. L’efficacité d’un circuit AQ dépend du temps de détection de l’avalanche, de sa contribution en charge au processus d’extinction, ainsi que de ses consommations d’espace et de puissance. Cette thèse vise à concevoir des circuits AQ capables de réduire efficacement l’effet d’ « afterpulsing » avec une faible consommation d’énergie et en occupant une surface minimale pour permettre ainsi le fonctionnement de pixels SPAD dans les applications à taux de comptage élevé. À cet égard, trois circuits AQ sont conçus avec différentes variations dans une technologie 28 nm CMOS FD-SOI. Les mesures expérimentales démontrent que ces circuits sont capables de réduire fortement l’effet d’ « afterpusling » tout en respectant les compromis mentionnés. De plus, la première intégration 3D monolithique de circuits AQ au-dessus d’une SPAD est présentée dans ce travail.

The integration of Single-Photon Avalanche Diodes (SPADs) in CMOS Fully Depleted Silicon-On-Insulator (FD-SOI) technology under a buried oxide (BOX) layer and a silicon film containing transistors makes it possible to realize a 3D SPAD at the chip level. In our study, a nanostructurated layer created by an optimized arrangement of Shallow Trench Isolation (STI) above the photosensitive zone generates constructive interferences and consequently an increase in the light sensitivity in the frontside illumination. A simulation methodology is presented that couples electrical and optical data in order to optimize the STI trenches (size and period) and to estimate the Photon Detection Probability (PDP) gain. Then, a test chip was designed, manufactured, and characterized, demonstrating the PDP improvement due to the STI nanostructuring while maintaining a comparable Dark Count Rate (DCR).