For multiphase voltage regulators (MPVRs) with conventional phase shedding and transient voltage clamping (TVC), transient response is limited by intrinsic clamping error, reduced converter loop feedback and phase shedding delay. To address the issues, this article proposes differentiation-triggered TVC (DTVC) and quasi-zero-delay phase shedding (QZDPS) schemes for joint transient enhancement of the MPVR. To eliminate the intrinsic clamping error, the DTVC scheme adopts a d v /d t circuit to detect output voltage differentiation in advance. Besides, converter load response is accelerated by saturated drive modulation in synchrony with the DTVC current injection. To take full advantage of multiphase current slew rate, the QZDPS is achieved with instant load estimation. Furthermore, to make DTVC compatible with QZDPS, the state transition logics for multiphase drive modulation are established with DTVC transient flags and QZDPS signal. It allows for a joint transient enhancement that pushes the load transient response of the MPVR to the physical boundary. According to experimental results, the proposed scheme improves the transient voltage deviation and response time by 38% and 75%, respectively. Along with the enhanced transient, the transient energy loss is reduced by 66%.

Recently, deep learning has enabled a huge leap forward in image inpainting. However, due to the memory and computational limitation, most existing methods are able to handle only low-resolution inputs, typically less than 1 K. With the improvement of Internet transmission capacity and mobile device cameras, the resolution of image and video sources available to users via the cloud or locally is increasing. For high-resolution images, the common inpainting methods simply upsample the inpainted result of the shrinked image to yield a blurry result. In recent years, there is an urgent need to reconstruct the missing high-frequency information in high-resolution images and generate sharp texture details. Hence, we propose a general deep learning framework for high-resolution image inpainting, which first hallucinates a semantically continuous blurred result using low-resolution inpainting and suppresses computational overhead. Then the sharp high-frequency details with original resolution are reconstructed using super-resolution refinement. Experimentally, our method achieves inspiring inpainting quality on 2K and 4K resolution images, ahead of the state-of-the-art high-resolution inpainting technique. This framework is expected to be popularized for high-resolution image editing tasks on personal computers and mobile devices in the future.

This paper presents a triple-mode average current control (TACC) strategy to achieve unity power factor and reduce the current stress for a boost PFC converter. The controller switches among different modes in each half-line cycle, and smooth transition is ensured by mapping of the operation region. By adaptive mode shifting, it reduces the current stress and current distortion caused by non-linear effects. With valley current shaping and comparisons, the TACC controller accordingly incorporates three control laws to adapt different modes. In discontinuous conduction mode (DCM), a variable on-time is calculated while the modulation is equivalent to PWM. In critical conduction mode (CRM), a constant on-time is derived, while the switching cycle is modified to regulate the current average value. For both DCM and CRM, the switching cycle is slightly extended to realize valley switching. Furthermore, with valley current shaping, the proposed controller reuses the CRM calculation to form continuous conduction mode (CCM) control law. To make the control laws compatible, normalized mapping and design rules are provided with respect to mode boundaries. This allows the TACC controller to automatically switch among different modes. Finally, experimental results prove the effectiveness of the controller in reducing the current stress and enlarging the preferable power range.

Power losses of switches and inductors are consistent challenges that hinder the development of high-frequency power supply in package (PSiP). This paper investigates the roadmap for power loss optimizations of switches and inductors in high-frequency PSiPs. Firstly, a size and parallel quantity design method to reduce power loss in an integrated Si LDMOSFET is provided with comprehensive consideration of switching frequency and power levels. Secondly, quality factors of different air-core inductors are analyzed with consideration of geometric parameters and skin effect, which provides the winding structure optimization to reduce power losses. The power losses of the integrated Si LDMOSFET and air-core inductors are both reduced to less than 10% of the output power at 1~100 MHz switching frequency and 0.1~10 W power level. Finally, based on the above optimizations, power losses of switches and inductors are calculated with switching frequency and power level. Combining the calculated results, this paper predicts the efficiency boundaries of PSiPs. Upon efficiency normalization with consideration of input and output voltage levels, all the predictions are consistent with the published literature. The efficiency predication error is 1~15% at 1~100 MHz switching frequency and 0.1~10 W power level. The above power loss optimizations improve the efficiency, which provides potential roadmaps for achieving high-frequency PSiPs.

Highly repetitive structures in IC, such as SRAM cells typically require extremely low failure ratio, making traditional Monte Carlo analysis extremely time consuming. Furthermore, the “curse of dimensionality” has become a major challenge for existing high-sigma yield analysis techniques. Thus, we propose a “sampling-training-substitution-verification” (STSV) yield analysis framework, which utilizes machine learning (ML) techniques to accelerate yield analysis in high-sigma and high-dimensional scenarios, effectively addresses the “curse of dimensionality.” In our framework, least absolute shrinkage and selection operator (Lasso) regression is adopted to substitute the mapping from process parameters to circuit performance, achieving high accuracy, and generalization. The model is adaptive for both low- and high-dimensional scenarios since the dimensional sparsity is achieved by $l1$ regularization. In addition, important process parameters can be identified by sparse feature weights of the Lasso model, which is of assistance for yield optimization. Compared with existing yield analysis techniques, the Lasso-based STSV framework offers great saving in a simulation program with integrated circuit emphasis (SPICE) cost, is attractive in high-dimensional demands.

Subtitles are crucial for video content understanding. However, a large amount of videos have only burned-in, hardcoded subtitles that prevent video re-editing, translation, etc. In this paper, we construct a deep-learning-based system for the inverse conversion of a burned-in subtitle video to a subtitle file and an inpainted video, by coupling three deep neural networks (CTPN, CRNN, and EdgeConnect). We evaluated the performance of the proposed method and found that the deep learning method achieved high-precision separation of the subtitles and video frames and significantly improved the video inpainting results compared to the existing methods. This research fills a gap in the application of deep learning to burned-in subtitle video reconstruction and is expected to be widely applied in the reconstruction and re-editing of videos with subtitles, advertisements, logos, and other occlusions.