Photonic crystal has been proved to manipulate light effectively and improve the performance of solar cells. In this paper, high-performance GaAs-based solar cells with photonic crystal were fabricated to decrease the dependence on the angle of incident light. Photoluminescence (PL) intensity of solar cells with photonic crystal reduced only 8% when the incident angle changed from 10° to 30°, while the PL intensity of the ordinary solar cells decreased 39% under the same condition. It manifests the photonic crystal can manipulate the incident light in turn reduce the dependence of incident light angle. Besides, the short circuit current of solar cells was increased by 32% after the photonic crystal was added. When the incident angle of light increased to 30° from 0°, the short circuit current of ordinary solar cell decreased 29.5%, while that of solar cell with photonic crystals reduced 12%. Correspondingly, the photoelectric conversion efficiency (PCE) of ordinary solar cells was reduced 31.2%. In contrast, solar cells with photonic crystal decreased only 11.5%. The enhancement factor of the PCE of solar cells with photonic crystal to that of ordinary solar cells increases from 1.26 to 1.6 as the incident angle rises to 30°from 0°. In summary, solar cells with photonic crystal are less sensitive to the incident angle and could absorb more light without angle limits, then increase the PCE. These solar cells with photonic crystals are promising in low-cost and high power conversion efficiency solar cell fields.

In this article, a honeycomb vertical surrounding gate access transistor array scheme is proposed to further decrease the DRAM cell area with aggressively shrink bit line (BL) pitch and word line (WL) pitch adopting the ZigZag BL and WL air gap. To verify the process feasibility, process flow emulation is optimized by virtual fabrication with SEMulator3D®. Moreover, the ZigZag BL feasibility in lithography process is evaluated by optical proximity correction (OPC) simulation. In addition, the parasitic capacitance of BL and WL decrease 22.8% and 76.8%, respectively, as compared to reference paper. And the electrical properties of the proposed device are simulated by three-dimensional technology computer aided design (3D TCAD). The GIDL effect is prohibited through prolonging the drain extension and reducing its doping concentration. Finally, the surrounding gate transistor can achieve high on-state current (>30 μA) at V _g =1.5 V and off-state current below 0.1 fA at V _d = -0.2 V. These results are beneficial for the direction of pathfinding for increasing the density and decreasing the energy consumption of DRAM.