Marek Jasinski

Prof. Dr. Marek Jasinski

Faculty of Electrical Engineering, Warsaw University of Technology, plac Politechniki 1, 00-661 Warszawa, Poland
orcid

Research Focus & Metrics

Academic Career Length

24Years (2003-Present)

(Calculated once Scilit publication data is synced: current year − year of first publication + 1)

Representative Publications

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5 April 2004 in IEEE Transactions on Industrial Electronics
Verified
Journal Article
Closed access
MMMariusz Malinowski
Mariusz Malinowski
MJMarek Jasinski
Marek Jasinski
MKM.P. Kazmierkowski
M.P. Kazmierkowski
This paper proposes a novel and simple direct power control of three-phase pulsewidth-modulated (PWM) rectifiers with constant switching frequency using space-vector modulation (DPC-SVM). The active and reactive powers are used as the pulse width modulated (PWM) control variables instead of the three-phase line currents being used. Moreover, line voltage sensors are replaced by a virtual flux estimator. The theoretical principle of this method is discussed. The steady-state and dynamic results of DPC-SVM that illustrate the operation and performance of the proposed system are presented. It is shown that DPC-SVM exhibits several features, such as a simple algorithm, good dynamic response, constant switching frequency, and particularly it provides sinusoidal line current when supply voltage is not ideal. Results have proven excellent performance and verify the validity of the proposed system.

19 April 2011 in IEEE Transactions on Industrial Informatics
Verified
Journal Article
Closed access
MKMarian P. Kazmierkowski
Marian P. Kazmierkowski
MJMarek Jasinski
Marek Jasinski
GWGrzegorz Wrona
Grzegorz Wrona
Power electronic Grid-Connected Converters (GCCs) are widely applied as grid interface in renewable energy sources. This paper proposes an extended Direct Power Control with Space Vector Modulation (DPC-SVM) scheme with improved operation performance under grid distortions. The real-time operated DPC-SVM scheme has to execute several important tasks as: space vector pulse width modulation, active and reactive power feedback control, grid current harmonics and voltage dips compensation. Thus, development and implementation of the DPC-SVM algorithm using single chip floating-point microcontroller TMS320F28335 is described. It combines large peripheral equipment, typical for microcontrollers, with high computation capacity characteristic for Digital Signal Processors (DSPs). The novelty of the proposed system lies in extension of the generic DPC-SVM scheme by additional higher harmonic and voltage dips compensation modules and implementation of the whole algorithm in a single chip floating point microcontroller. Overview of the laboratory setup, description of basic algorithm subtasks sequence, software optimization as well as execution time of specific program modules on fixed-point and floating-point processors are discussed. Selected oscillograms illustrating operation and robustness of the developed algorithm used in 5 kVA laboratory model of the GCC are presented.

25 March 2010 in IEEE Industrial Electronics Magazine
Verified
Journal Article
Open access
Giovanni SpagnuoloGiovanni Spagnuolo
Giovanni Spagnuolo
Giovanni PetroneGiovanni Petrone
Giovanni Petrone
SAS. V. Araujo
S. V. Araujo
CCC. Cecati
C. Cecati
EFE. Friis-Madsen
E. Friis-Madsen
PZP. Zacharias
P. Zacharias
A short summary of some speeches given during Seminar on Renewable Energy system (SERENE) is presented. The contributions have been mainly focused on power electronics for photovoltaic (PV) and sea wave energies, pointing out some aspects related to efficiency, reliability, and grid integration. Finally, main issues concerning fuel cell (FC) systems as generators based on hydrogen as a low environmental impact energy vector are presented.

1 March 2016 in IEEE Transactions on Industrial Electronics
Verified
Journal Article
Closed access
KAKamil Antoniewicz
Kamil Antoniewicz
MJMarek Jasinski
Marek Jasinski
MKMarian P. Kazmierkowski
Marian P. Kazmierkowski
MMMariusz Malinowski
Mariusz Malinowski
This paper presents the new implementation of the finite control states set model predictive control (FS-MPC) applied to three-level four-leg flying capacitor converter (FCC) operating as a shunt active power filter (SAPF). The three main issues regarding the algorithm development are described and the solutions are proposed. The first is addressed to modeling of the four-wire system, which for simplification is based on wire-to-wire voltage equations. The second relates to the control of FCC by MPC, i.e., a proper interpretation of the FCC switching states and control of flying capacitor (FC) voltages, which was moved from the prediction loop. Finally, the system restriction regarding undesirable switching states' transitions is explained and the solution is presented. The control performance was tested in the simulation model in MATLAB-Simulink and validated experimentally by measurements on the 10-kVA FCC laboratory setup.

21 August 2020 in IEEE Transactions on Power Electronics
Verified
Journal Article
Closed access
SBSebastian Bąba
Sebastian Bąba
AGAndrzej Gieraltowski
Andrzej Gieraltowski
MJMarek Jasinski
Marek Jasinski
Frede BlaabjergFrede Blaabjerg
Frede Blaabjerg
ABAmir Sajjad Bahman
Amir Sajjad Bahman
MZMarcin Zelechowski
Marcin Zelechowski
One way to achieve the best in class reliability is the implementation of a Design for Reliability methodology into the design process in order to estimate the lifetime of each individual critical component, based on proper reliability models for failure modes. The main drawback of above-mentioned approach is that it is relying on handbook-based reliability models, which usually are accurate only for particular components. This fact causes a necessity to develop a testing procedure for SiC power MOSFET, to determine its reliability model parameters. Such model could be further implemented in the Design for Reliability methodology for high performance power supplies design process. In this paper, a cost effective and industrial friendly laboratory setup for Active Power Cycling of SiC power MOSFETs in SOT-227b housing is presented. By this example, various control strategies for accelerated lifetime testing, degradation indicators for wear out condition monitoring and junction temperature estimation methods are compared on their impact on test results and complexity in either laboratory setup and its maintenance procedure. Technical issues related to start up of Active Power Cycling test and failure detection algorithm are discussed. At last, test results for SiC power MOSFETs subjected to over 63355 power cycles are presented.

1 December 2011 in Bulletin Of The Polish Academy Of Sciences-Technical Sciences
Verified
Journal Article
Open access
PDF file
MBM. Bobrowska-Rafal
M. Bobrowska-Rafal
KRKrzysztof Rafal
Krzysztof Rafal
MJMarek Jasinski
Marek Jasinski
MKM. Kazmierkowski
M. Kazmierkowski
Grid synchronization and symmetrical components extraction with PLL algorithm for grid connected power electronic converters - a review: In this paper, a review of Phase Locked Loop (PLL) algorithms and symmetrical component extraction methods intended for grid-connected power electronic converters are presented. Proposed classification is based on voltage representation in three coordinates: natural (abc), stationary (αβ) and rotating coordinates (dq). The three selected algorithms are described in details: Dual Second Order Generalized Integrator (DSOGI-PLL), Dual Virtual Flux - both in stationary coordinates. The third one, in rotating dq coordinates, is Dual Synchronous Reference Frame PLL (DSRF-PLL). A comparison of PLL algorithms is presented. Also, selected experimental results are given to verify practical application of discussed algorithms.