Lithium-ion (Li-ion) batteries have increasingly been used in diverse applications. Accurate estimation of the state of health (SOH) of the Li-ion batteries is vital for all stakeholders and critical in various applications such as electric vehicles (EVs). The electrical equivalent circuit (EEC) 2-RC model is often used to model the battery operation but has not been used to capture the degradation of battery cells over time. This paper uses the 2-RC model to capture the degradation of the Li-ion battery. The proposed model is not only time-dependent but also captures the effect of temperature on battery degradation. The proposed approach estimates the SOH accurately and is also considerably flexible for diverse cells of different chemistry. We further generalize an N-RC model approach to evaluate the SOH of the battery. We compare the proposed model (2-RC) with the 1-RC model, and through numerical results, we show that the 2-RC model outperforms 1-RC and reduces the computational cost significantly. Similarly, the 2-RC model outperforms 3-RC and higher-order circuits. We also show that the proposed approach can capture the battery dynamics better for specific smaller orders of the polynomial (associated with Arrhenius equation) when compared with the 1-RC approach with considerably reduced (up to 60%) root mean square error (RMSE). Lastly, the average testing RMSE for 2-RC is 52.4%.

Grid-connected rooftop and ground-mounted solar photovoltaics (PV) systems have gained attraction globally in recent years due to (a) reduced PV module prices, (b) maturing inverter technology, and (c) incentives through feed-in tariff (FiT) or net metering. The large penetration of grid-connected PVs coupled with nonlinear loads and bidirectional power flows impacts grid voltage levels and total harmonic distortion (THD) at the low-voltage (LV) distribution feeder. In this study, LV power quality issues with significant nonlinear loads were evaluated at the point of common coupling (PCC). Various cases of PV penetration (0 to 100%) were evaluated for practical feeder data in a weak grid environment and tested at the radial modified IEEE-34 bus system to evaluate total harmonic distortion in the current (THD_i) and voltage (THD_v) at PCC along with the seasonal variations. Results showed lower active, reactive, and apparent power losses of 1.9, 2.6, and 3.3%, respectively, with 50% solar PV penetration in the LV network as the voltage profile of the LV network was significantly improved compared to the base case of no solar. Further, with 50% PV penetration, THD_i and THD_v at PCC were noted as 10.2 and 5.2%, respectively, which is within the IEEE benchmarks at LV.

This article introduces a new transformerless ac-dc-ac converter topology suitable for a high-power-density high-frequency single-phase online uninterruptible power supply (UPS) with a common neutral between the input and output ac ports. The proposed converter comprises an input power factor correction rectification (ac-dc) stage which is followed by an inversion (dc-ac) stage. The rectification stage operates in boost mode during the input positive half line cycle and buck-boost mode during the input negative half line cycle, while the inversion stage operates in buck and buck-boost modes in the output positive and negative half line cycles, respectively. The rectification stage utilizes boundary conduction mode control enabling soft-switching and allowing high-frequency operation. The inversion stage is operated in continuous conduction mode, wherein a digital controller regulates the output voltage of the converter across both resistive and reactive loads. The proposed online UPS utilizes a single (nonsplit) dc-bus between the rectification and inversion stages, resulting in a 50% reduction in dc-bus capacitance requirement compared to conventional split-bus online UPS topologies. Additionally, two battery interface solutions are also investigated which provide a trade-off between passive volume and additional switch-count. To verify the performance and control of the proposed online UPS, a GaN-based electrolytic-free 1-kVA prototype online UPS is designed, built, and tested. The prototype ac-dc-ac converter achieves a peak efficiency of 95.2% and maintains a high efficiency of above 92.3% across the full output power range. The electrolytic-free prototype ac-dc-ac converter for the online UPS achieves a power density of 26.4 W/in ³ .

Renewable energy incorporation in many countries takes different forms. In many developed countries, grid-tied solar photovoltaic (PV) installations are widely coupled with lucrative Feed-in-Tariffs (FiT). However, conventional grid-tied solutions are not readily viable in many developing countries mainly due to intermittent grids with load shedding and, in some cases, lack of net-metering or FiT. Load shedding refers to an intentional electrical power shutdown by the utility company where electricity delivery is stopped for non-overlapping periods of time over different parts of the distribution region. This results in a non-continuous availability of the utility grid for many consumers over the course of a day. In this work, the key challenges in the integration of solar energy explicitly in residential power back-up units are reviewed and system hardware level requirements to allow optimized solar PV utilization in such intermittent grid environments are analyzed. Further, based upon the low-cost sensing and real-time monitoring scheme, an online optimization framework enabling efficient solar incorporation in existing systems to achieve minimum grid dependence in intermittent grid environments is also provided. This work is particularly targeted for over 1.5 billion residents of semi-electrified regions in South Asia and Africa with the weak and intermittent grid.

This paper proposes an analytical formulation-based minimization of DC link current ripples for interleaved parallel inverter systems. Parallel inverter systems find applications in multiple fields. The interleaved superposition of the DC link currents in these systems can potentially be adjusted to mitigate the overall harmonics consequently reducing the DC link capacitor size. To this end, a widely used approach in the literature is the Fourier analysis based on interleaving focusing on dominant harmonic mitigation. However, it leaves room for a generic analytical mechanism to provide time shifts leading to an optimal reduction in DC-link ripples. The goal of this work is to target this optimal reduction by utilizing an analytical mechanism. The paper presents an alternate way of DC-link formulation in terms of the piece-wise sinusoids of inverter output currents for space vector modulation-based systems. The formulation is then used to numerically optimize the interleaved shifts for minimum ripples. Moreover, in addition to the traditional concept of fixed time interleaving, a contemporary concept of sequence-based interleaving is utilized, which is anticipated to have more flexibility in the implementation and additional switching synchronism with PWM rectifiers for back–back converters. Therefore, the sequence interleaving has also been utilized in conjunction with the proposed ripple reduction methodology. Further, an underexplored area of using the combined impact of sequence and time interleaving has also been applied in this work. These interleaving methods are shown to provide significantly improved DC-link ripple mitigation, as compared to existing methods, using numerical assessment followed by simulations and experimental evaluation.

DC-link current harmonics and common mode voltage (CMV) are key design challenges for inverter-based power electronic systems. Addressing them collectively without additional hardware and/or complexity has promising advantages. This article investigates the interleaved utilization of modified space vector PWM schemes for parallel-inverter systems, targeting a combined and simultaneous reduction of these quality concerns. A time-domain analytical dc-link current formulation and a new application of sequence-based interleaving are combined in an offline numerical optimization algorithm that locates optimal interleaving shifts synced with the PWM sequence. With simulation and experimental validation, the corresponding numerical results ascertain an effective suppression of dc-link current harmonics alongside CMV reduction. In addition, this article extends the proposed idea to a special application for 3xmultiphase machines through experimental validation.