In this article, we proposed an analytical model based on charge distribution for switched-capacitor trans-impedance amplifiers (SCTIAs). The changes in the load state of the amplifier under different operating conditions and the influence of the gain of the operational amplifier (Opamp) on the trans-impedance gain are analyzed to improve the design theory of switched-capacitor trans-impedance amplifiers. According to the conclusion drawn from the analysis, the trans-impedance amplifier (TIA) has been designed by adopting “correlated double sampling technology” and “cross-connection technology” to optimize input-referred noise current, power consumption, and trans-impedance gain. As a result, the trans-impedance gain reaches up to 206 dB, while the bandwidth is 3 kHz. The current readout system achieves an input-referred noise current floor of 2.96 $fA/\sqrt{Hz}$ at 1 kHz, and the power consumption of the system is 0.643 mW. The circuit has been simulated with the technology of 0.18 μm, and the layout area is 1000 μm × 500 μm.

This article proposes a second-order switch-capacitor filter that integrates low-pass, high-pass, band-pass, band-stop, and all-pass, and achieves flexible bandwidth adjustment of the filter through clock rate and capacitance ratio. The final filter design consists of two completely independent second-order switch-capacitor filter channels, and a 4-order Butterworth low-pass filter is designed through two-stage cascades. The two completely independent second-order switch-capacitor filters are integrated on a single chip and manufactured using the Huahong BCD350GE high-voltage 24 V process. The measurement results indicate that the proposed switch-capacitor filter achieves various functional filtering characteristics and achieves a bandwidth of 5 Hz to 10 kHz. The chip area is 5.1 × 3.1 mm${}^2$, powered by a dual power supply of ± 5 V, and the power consumption is 80 mW.

A balise is a specialized device utilized for train communication and control. However, existing balises are composed of separate components, resulting in high production costs, low integration, and significant room for improvement in stability. We propose an integrated solution, to enhance the integration of balises, reducing the number of discrete components. Additionally, we propose a feedback-enabled energy extraction circuit with a limiter-based startup circuit, to enhance the stability of the balise system. The prototype was fabricated using 180 nm high voltage(HV) complementary metal oxide semiconductor(CMOS) technology. Once implemented in the balise, the number of discrete components in the system is reduced by 25%, and the system can start up within 20 ms and operate stably. The mean data rate (MDR) deviation of the balise is only 62 ppm, which is 69% lower than that specified in the test specification for the Eurobalise form–fit–function interface specification (FFFIS), and the maximum time interval error (MTIE) is less than 250 ns.

This study presents a sample isolation bridge readout integrated circuit (ROIC) specifically designed for intracranial pressure (ICP) monitoring systems. The ROIC consists of an instrumentation amplifier (IA) and a successive approximation register (SAR) analog-to-digital converter (ADC). Additionally, the output of the IA is isolated to protect against output spikes that could compromise the linearity and stability of the ROIC. Both traditional and proposed ROIC circuits are fabricated using 0.18 µm complementary metal-oxide-semiconductor (CMOS) technology. The peak signal-to-noise ratio (SNR) for the traditional ROIC is 40.9 dB, while the peak signal-to-noise and distortion ratio (SNDR) is measured at 40.1 dB. In contrast, the proposed ROIC, which incorporates the SAR ADC, achieves a peak SNR of 54.6 dB and a peak SNDR of 51.8 dB, demonstrating a significant improvement in linearity. The new ROIC consumes 39.5 µA of current from a 1.8 V power supply and occupies a chip core area of only 0.27 mm².

This paper presents a fully integrated passive self-jamming cancellation (SJC) circuit in 0.18 µm Complementary Metal Oxide Semiconductor (CMOS) technology for ultra-high frequency (UHF) radio frequency identification (RFID) applications. Based on the active amplitude and phase control, a novel passive variable capacitor array and signal combiner are adopted instead of a traditional variable amplifier/attenuator and a phase shifter to reduce the circuit complexity and thus achieve higher linearity and low noise. We use an improved cancellation algorithm based on the local search method to quickly and accurately find the cancellation point that minimizes the self-jamming signal power. The simulation and measurement results are constant, and a suppression of 38 dB can be achieved in the working frequency of 860–960 MHz. The cancellation algorithm can be finished within 0.5 ms. These results indicate that the designed SJC circuit can be a promising candidate for UHF RFID applications.