The decreasing-width, increasing-aspect-ratio RDL presents significant challenges to the design for reliability (DFR) of an advanced package. Therefore, this paper proposes an ML-based RDL modeling and simulation method. In the method, RDL was divided into blocks and subdivided into pixels of metal percentage, and the RDL was digitalized as tensors. Then, an ANN-based surrogate model was built and trained using a subset of tensors to predict the equivalent material properties of each block. Lastly, all blocks were transformed into elements for simulations. For validation, line bending simulations were conducted on an RDL, with the reaction force as an accuracy indicator. The results show that neglecting layout impact caused critical errors as the substrate thinned. According to the method, the reaction force error was 2.81% and the layout impact could be accurately considered with 200 × 200 elements. For application, the TCT maximum temperature state simulation was conducted on a CPU chip. The simulation indicated that for an advanced package, the maximum stress was more likely to occur in RDL rather than in bumps; both RDL and bumps were critically impacted by layouts, and RDL stress was also impacted by vias/bumps. The proposed method precisely concerned layout impacts with few resources, presenting an opportunity for efficient improvement.

The development of chip manufacturing and advanced packaging technologies has significantly changed redistribution layers (RDLs), leading to shrinking line width/spacing, increasing the number of build-up layers and package size, and introducing organic materials such as polyimide (PI) for dielectrics. The fineness and complexity of structures, combined with the temperature-dependent and viscoelastic properties of organic materials, make it increasingly difficult to predict the thermo-mechanical behavior of wafer-level Cu-PI RDL structures, posing a severe challenge in warpage prediction. This study models and simulates the thermo-mechanical response during the manufacturing process of Cu-PI RDL at the wafer level. A cross-scale wafer-level equivalent model was constructed using a two-level partitioning method, while the PI material properties were extracted via inverse fitting based on thermal warpage measurements. The warpage prediction results were compared against experimental data using the maximum warpage as the indicator to validate the extracted PI properties, yielding errors under less than 10% at typical process temperatures. The contribution of RDL build-up, wafer backgrinding, chemical mechanical polishing (CMP), and through-silicon via (TSV)/through-glass via (TGV) interposers to the warpage was also analyzed through simulation, providing insight for process risk evaluation. Finally, an artificial neural network was developed to correlate the copper ratios of four RDLs with the wafer warpages for a specific process scenario, demonstrating the potential for wafer-level warpage control through copper ratio regulation in RDLs.

Due to the demand for high reliability and thermal conductivity of high-power modules operating at high temperatures, sintered nano-silver (Ag) has garnered significant attention as an excellent interconnect and heat transfer layer, particularly for its thermal conductivity and other reliability research. Since the mechanical behavior and heat conduction capacity of sintered Ag is generally regulated by changes in temperature, its microstructure will change accordingly, affecting its performance. In this study, a machine learning model was used to evaluate and predict the thermal conductivity of sintered Ag, providing an effective method to analyze the influence of microstructural characteristics on its heat transfer properties. Image processing and model simulation of scanning electron microscopy images of sintered nano-Ag nanostructures were performed using MATLAB and Ansys software. A batch calculation of the thermal conductivity of 2D images of sintered nano-Ag nanostructures was performed to obtain sufficient data sets. Based on the artificial neural network model of Bayesian optimization, the equivalent thermal conductivity of different sintered nano-Ag microstructures was predicted with high accuracy using the microstructure image and characteristic parameters of sintered nano-Ag. The proposed method enables rapid, effective, and accurate evaluation and prediction of the thermal conductivity of sintered nano-Ag, contributing significantly to the reliability of power modules.

High-speed digital microsystems has emerged as one of the most important solutions for improving system performance, bandwidth, and power consumption. Based on mature micro-system processing technology, a material extraction approach for silicon interposer applied for high-speed digital microsystems was presented in order to obtain frequency-dependent precise material parameters. By combining microwave theory and mathematical model of iterative algorithm, the dielectric constant (Dk) and the dissipation factor (Df) of polyimide dielectric layer is acquired, which minimizes testing costs and streamlines testing process. The method is based on two-port transmission/reflection measurements. Vector Network Analyzer (VNA) is used to extract the scattering parameters with an extraction range of 1 MHz to 10 GHz. The algorithm is programmed using MATLAB. The observed Dk values at 2 GHz, 6 GHz, 8 GHz, and 10 GHz are, respectively, 3.22, 3.04, 2.96, 3.03, and 2.91, while the corresponding Df values are 0.021, 0.025, 0.026, 0.026, and 0.024. Finally, the complex permittivity derived is simulated and analyzed using Ansys HFSS. The results verify the validity of the theoretical method and proves that the values of the complex permittivity obtained by the method in this paper are reliable.

The development of chip manufacturing and advanced packaging technologies has significantly changed redistribution layers (RDLs), leading to shrinking line width/spacing, increasing the number of build-up layers and package size, and introducing organic materials such as polyimide (PI) for dielectric. The fineness and complexity of structures, combined with the temperature-dependent and viscoplastic properties of organic materials, make it increasingly difficult to predict the thermo-mechanical behavior of wafer-level Cu-PI RDL structures, posing a severe challenge in warpage prediction. This study models and simulates the thermo-mechanical response during the manufacturing process of Cu-PI RDL at the wafer level. A cross-scale wafer-level equivalent model was constructed using a two-level partitioning method, while PI material properties were extracted via inverse fitting based on thermal warpage measurements. Warpage prediction results were compared against experimental data using maximum warpage as the indicator to validate the extracted PI properties, yielding errors under less than 10% at typical process temperatures. The contribution of RDL build-up, wafer backgrinding, chemical mechanical polishing (CMP), and TSV/TGV interposers to the warpage was also analyzed through simulation, providing insight for process risk evaluation. Finally, an artificial neural network was developed to correlate copper ratios of four RDL layers with wafer warpages for a specific process scenario, offering a potential direction for layout design optimization.

The microstructure is an important key factor for the reliability of deep through silicon via (TSV) electroplated copper. In the present study, the influence of current density on the surface physical field and microstructure in the electroplated copper were discussed using a combined method of numerical simulation and experiment. The results showed that the optimal electroplated parameters with the defect-free filling were confirmed to be at 0.1-0.17 Ampere per Square Decimeter (ASD) with an accelerator-to-suppressor ratio of 1:10 when the size of deep TSV was Φ20 μm × 200 μm with an aspect ratio of 10:1. The microstructure of TSVs exhibited a distinct distribution feature: fine grains along sidewalls and at the mouth, large columnar grains in mid-regions, and equiaxed grains at the bottom. The grain size and the quantity of Σ3 twin boundaries first decreased and then increased with increasing current density due to the competing effect of nucleation rate and grain growth by governing the polarization and suppressor desorption. Moreover, the intermediate 9R structure between the matrix and the twin was first observed in the electroplated copper, which provided a new way for strain accommodation in deep TSV electroplated copper, and the matrix→9R→twin pathway was proposed through the slip of Shockley partial dislocations. These findings served as a valuable reference for modeling microstructure evolution and laid a foundation for both microstructure prediction and control in deep TSV electroplated copper.