The decreasing-width, increasing-aspect-ratio RDL presents significant challenges to the design for reliability (DFR) of an advanced package. Therefore, this paper proposes an ML-based RDL modeling and simulation method. In the method, RDL was divided into blocks and subdivided into pixels of metal percentage, and the RDL was digitalized as tensors. Then, an ANN-based surrogate model was built and trained using a subset of tensors to predict the equivalent material properties of each block. Lastly, all blocks were transformed into elements for simulations. For validation, line bending simulations were conducted on an RDL, with the reaction force as an accuracy indicator. The results show that neglecting layout impact caused critical errors as the substrate thinned. According to the method, the reaction force error was 2.81% and the layout impact could be accurately considered with 200 × 200 elements. For application, the TCT maximum temperature state simulation was conducted on a CPU chip. The simulation indicated that for an advanced package, the maximum stress was more likely to occur in RDL rather than in bumps; both RDL and bumps were critically impacted by layouts, and RDL stress was also impacted by vias/bumps. The proposed method precisely concerned layout impacts with few resources, presenting an opportunity for efficient improvement.

The microfluidic device (MFD) with a glass–PDMS–glass (G-P-G) structure is of interest for a wide range of applications. However, G-P-G MFD fabrication with an ultra-thin PDMS film (especially thickness less than 200 μm) is still a big challenge because the ultra-thin PDMS film is easily deformed, curled, and damaged during demolding and transferring. This study aimed to report a thickness-controllable and low-cost fabrication process of the G-P-G MFD with an ultra-thin PDMS film based on a flexible mold peel-off process. A patterned photoresist layer was deposited on a polyethylene terephthalate (PET) film to fabricate a flexible mold that could be demolded softly to achieve a rigid structure of the glass–PDMS film. The thickness of ultra-thin patterned PDMS could reach less than 50 μm without damage to the PDMS film. The MFD showcased the excellent property of water evaporation inhibition (water loss < 10%) during PCR thermal cycling because of the ultra-thin PDMS film. Its low-cost fabrication process and excellent water evaporation inhibition present extremely high prospects for digital PCR application.

The development of chip manufacturing and advanced packaging technologies has significantly changed redistribution layers (RDLs), leading to shrinking line width/spacing, increasing the number of build-up layers and package size, and introducing organic materials such as polyimide (PI) for dielectrics. The fineness and complexity of structures, combined with the temperature-dependent and viscoelastic properties of organic materials, make it increasingly difficult to predict the thermo-mechanical behavior of wafer-level Cu-PI RDL structures, posing a severe challenge in warpage prediction. This study models and simulates the thermo-mechanical response during the manufacturing process of Cu-PI RDL at the wafer level. A cross-scale wafer-level equivalent model was constructed using a two-level partitioning method, while the PI material properties were extracted via inverse fitting based on thermal warpage measurements. The warpage prediction results were compared against experimental data using the maximum warpage as the indicator to validate the extracted PI properties, yielding errors under less than 10% at typical process temperatures. The contribution of RDL build-up, wafer backgrinding, chemical mechanical polishing (CMP), and through-silicon via (TSV)/through-glass via (TGV) interposers to the warpage was also analyzed through simulation, providing insight for process risk evaluation. Finally, an artificial neural network was developed to correlate the copper ratios of four RDLs with the wafer warpages for a specific process scenario, demonstrating the potential for wafer-level warpage control through copper ratio regulation in RDLs.

The decreasing width, increasing aspect ratio RDL presents significant challenges to design for reliability (DFR) of advanced package. Therefore, this paper proposes a ML based RDL modeling and simulation method. In the method, RDL is divided into blocks and subdivided into pixels of metal percentage, and the RDL is digitalized as tensors. Then, an ANN-based surrogate model is built and trained by a subset of tensors to predict the equivalent material properties of each block. Lastly, all blocks are transformed into elements for simulations. For validation, line bending simulations were conducted on an RDL, with the reaction force as accuracy indicator. The results show that neglecting layout impact causes critical errors as substrate thins. By the method, the reaction force error is 2.81% and the layout impact can accurately be considered with 200×200 elements. For application, the TCT maximum temperature state simulation was conducted on a CPU chip. The simulation indicates that for advanced package the maximum stress more likely occurs in RDL rather than bumps, both RDL and bumps are critical impacted by layouts, and RDL stress is also impacted by vias/bumps. The proposed method precisely concerns layout impacts with little resources, presents an opportunity of efficiency improvement.

The development of chip manufacturing and advanced packaging technologies has significantly changed redistribution layers (RDLs), leading to shrinking line width/spacing, increasing the number of build-up layers and package size, and introducing organic materials such as polyimide (PI) for dielectric. The fineness and complexity of structures, combined with the temperature-dependent and viscoplastic properties of organic materials, make it increasingly difficult to predict the thermo-mechanical behavior of wafer-level Cu-PI RDL structures, posing a severe challenge in warpage prediction. This study models and simulates the thermo-mechanical response during the manufacturing process of Cu-PI RDL at the wafer level. A cross-scale wafer-level equivalent model was constructed using a two-level partitioning method, while PI material properties were extracted via inverse fitting based on thermal warpage measurements. Warpage prediction results were compared against experimental data using maximum warpage as the indicator to validate the extracted PI properties, yielding errors under less than 10% at typical process temperatures. The contribution of RDL build-up, wafer backgrinding, chemical mechanical polishing (CMP), and TSV/TGV interposers to the warpage was also analyzed through simulation, providing insight for process risk evaluation. Finally, an artificial neural network was developed to correlate copper ratios of four RDL layers with wafer warpages for a specific process scenario, offering a potential direction for layout design optimization.