An enhanced single-stage folded cascode operational transconductance amplifier able to drive large capacitive loads is presented. Circuits that adaptively bias the input differential pair and the current folding stage are employed, which provide class AB operation with dynamic current boosting and increased gain-bandwidth (GBW) product. Measurement results of a test chip prototype fabricated in a 0.5-μm CMOS process show an increase in slew rate and GBW by a factor of 30 and 15, respectively, versus the class A version using the same supply voltage and bias currents. Overhead in other performance metrics is small.

An enhanced super class AB recycling folded cascode operational transconductance amplifier is presented. It combines various adaptive biasing and transconductance enhancement techniques. Measurement results of a CMOS 130 nm test chip prototype show an improvement in slew rate and gain-bandwidth product by factors 100 and 27, respectively, compared to the conventional recycling folded cascode topology for the same supply voltage and bias currents.

A novel approach to design low-power area-efficient rail-to-rail output single-stage class-AB operational transconductance amplifiers (OTAs) with enhanced large-and small-signal performance to drive large capacitive loads is presented. It is based on a non-linear nested current mirror at the active load of a splitted differential input pair biased in weak inversion that boosts dynamic currents beyond their quiescent value directly at the output branch. As a result, slew rate, DC gain, gain-bandwidth product, settling time and noise performance are improved without additional circuit elements or power consumption. An OTA prototype has been fabricated in a 180-nm CMOS process, consuming a quiescent power of 2.9 $\mu$ W from a supply voltage of $\pm$ 0.5 V and a silicon area of 0.001 mm $^{2}$ . Measurement results validate the advantages of the proposal, exhibiting positive and negative slew rates of 110 V/ms and $-$ 58 V/ms, respectively, and a gain-bandwidth product of 136 kHz with a phase margin of 90 $^{\circ}$ for a capacitive load of 160 pF.

A current-mode CMOS RMS-DC converter is presented. The basic building blocks are based on a novel approach to design current-mode computational cells. In such an approach, the large-signal V-I characteristic of class-AB transconductors is conveniently exploited leading to a very regular and compact implementation. A proper biasing scheme in such transconductors allows operation with supply voltage as low as V/sub GS/+2V/sub DSsat/. Measurement results from a practical prototype are presented in order to demonstrate the technique proposed here.

A novel square-root domain (SRD) second order filter with automatic tuning control is described. The tuning system is based on a master-slave configuration, where the master is a SRD current-mode magnitude locked loop. The control circuitry allows tuning of the cut-off frequency as well as the quality factor and gain of the filter. The basic building blocks of the complete system are implemented employing a design strategy based on the inherent nonlinear characteristic of Class-AB linear transconductors. A proper biasing scheme in such transconductors leads to operation with very low supply voltages (as low as V/sub GS/+2V/sub DSsat/). Simulation and numerical results together with measurements from a fabricated prototype in a 0.8-/spl mu/m CMOS technology are included in order to validate the design technique proposed.

A new approach to design super class AB operational transconductance amplifiers (OTAs) with enhanced large-signal and small-signal performance is presented. It is based on employing two nested positive and negative feedback loops at the active load of an adaptively biased differential pair in weak inversion region. As a result, DC gain, gain-bandwidth product, settling time and noise are improved compared to conventional super class AB OTAs without extra circuit nodes or power consumption. Measurement results of a 180 nm CMOS test chip prototype show a current boosting factor higher than 5000 and a nearly ideal current efficiency. Due to the ultra-low quiescent currents and high driving capability, the circuit exhibits an excellent large-signal figure-of-merit (FOM _L ) of 236 V ^-1 . To illustrate the applicability of the proposed approach, a differential sample-and-hold (S/H) circuit was designed and fabricated on the same test chip. Measurement results of the S/H validate the advantages of the proposal.