Lately, there has been significant progress in the field of wireless communications and networking. Furthermore, the number of applications that require context information as the user's location will increase in the coming years. However, this issue still has not been solved indoors due to the RF (Radio Frequency) signals' behaviour in this kind of scenarios. In this paper, we present a robust, easy to deploy and flexible indoor localization system based on ZigBee Wireless Sensor Networks. It is important to mention that our localization system is based on RSSI (Received Signal Strength Indicator) level measurements since this information can be obtained directly from the messages exchanged between nodes, so no extra hardware is required. Our localization system consists of two phases: calibration and localization. Anytime a blind node needs to be located, our system performs calibration using a matrices system, so that the environment can be characterized, taking into account possible changes on it since the last request. Then, in the localization phase, the central server processes all the information and calculates the blind node's position with the new iterative algorithm we present. With this indoor positioning algorithm we can estimate the blind node's position with a good resolution (3 m average error), so we can say that this ZigBee localization algorithm provides very promising results.

Inferring faults throughout the power grid involves fast calculation, large scale of data, and low latency. Our heterogeneous architecture in the edge offers such high computing performance and throughput using an Artificial Intelligence (AI) core deployed in the Alveo accelerator. In addition, we have described the process of porting standard AI models to Vitis AI and discussed its limitations and possible implications. During validation, we designed and trained some AI models for fast fault detection in Smart Grids. However, the AI framework is standard, and adapting the models to Field Programmable Gate Arrays (FPGA) has demanded a series of transformation processes. Compared with the Graphics Processing Unit platform, our implementation on the FPGA accelerator consumes less energy and achieves lower latency. Finally, our system balances inference accuracy, on-chip resources consumed, computing performance, and throughput. Even with grid data sampling rates as high as 800,000 per second, our hardware architecture can simultaneously process up to 7 data streams.

There are different experiences in the use of RFID technology for warehouse inventories. However, there is future work to do on the design of advanced reading devices, applying wearable computation techniques and wireless communications. The aim of this work is to allow a natural interaction for the user who performs inventory tasks. In this paper we show the RFIDGlove system, which consists of a glove with an integrated RFID reader, an organic micro display and a communication system. The RFIDGlove system increases the efficiency of the activities in these areas, improving the user's experience and comfort while he/she uses the system.

Smart grid endpoints need to use two environments within a processing system (PS), one with a Linux-type operating system (OS) using the Arm Cortex-A53 cores for management tasks, and the other with a standalone execution or a real-time OS using the Arm Cortex-R5 cores. The Xen hypervisor and the OpenAMP framework allow this, but they may introduce a delay in the system, and some messages in the smart grid need a latency lower than 3 ms. In this paper, the Linux thread latencies are characterized by the Cyclictest tool. It is shown that when Xen hypervisor is used, this scenario is not suitable for the smart grid as it does not meet the 3 ms timing constraint. Then, standalone execution as the real-time part is evaluated, measuring the delay to handle an interrupt created in programmable logic (PL). The standalone application was run in A53 and R5 cores, with Xen hypervisor and OpenAMP framework. These scenarios all met the 3 ms constraint. The main contribution of the present work is the detailed characterization of each real-time execution, in order to facilitate selecting the most suitable one for each application.

The use of hypervisors is constantly growing on account of their benefits. For some applications with hard realtime constraints, it is interesting to analyze the speed reduction that could cause. MPSoC boards are suitable for the use of hypervisors thanks to having an FPGA which allows the user to design the hardware and Cortex A53 cores, with armv8 architecture, which have virtualization extensions. The board has been validated with Xen hypervisor. This paper compares five scenarios to characterize the impact of the hypervisor layer on the speed of a network connection: a standalone application, Petalinux directly running on hardware, Petalinux running in Xen Dom0, Petalinux running in Xen DomU paravirtualizing the network and a Petalinux running in Xen DomU pass-throughing the network. It also characterizes the delay of the network connection in some scenarios as a complementary measurement. All the cases are implemented in the Zynq ZCU102 board. It is shown that a Xen hypervisor layer creates a considerable reduction in network speed. Provided that the network is settled down in passthrough mode, the network speed in DomU is almost the same as if there was no hypervisor.

IEEE 1588, also known as the Precision Time Protocol (PTP), is a standard protocol for clock synchronization in distributed systems. While it is not architecture-specific, implementing IEEE 1588 on Reduced Instruction Set Computer-V (RISC-V) low-power embedded devices demands considering the system requirements and available resources. This paper explores various approaches and techniques to achieve accurate time synchronization in such instruments. The analysis covers software and hardware implementations, discussing each method’s challenges, benefits, and trade-offs. By examining the state-of-the-art in this field, this paper provides valuable insights and guidance for researchers and engineers working on time-critical applications in RISC-V-based embedded systems, aiding in selecting the most-suitable stack for their designs.