Non-volatile computing-in-memory (nvCIM) can potentially meet the ever-increasing demands on improving the energy efficiency (EF) for intelligent edge devices. However, it still suffers from limited input parallelism due to the parasitic effects, signal margin degradation due to device non-idealities, and large hardware cost for analog readout. In this work, we present a two-transistor-one-resistor (2T1R) resistive memory (RRAM) nvCIM macro featuring: 1) a macro structure with decoupled memory and computing data paths; 2) the weighted hybrid 2T1R (WH-2T1R) cell array; 3) the redundant sub-array mapping scheme of the most-significant-bit (RSM-MSB); and 4) reference-subtracting current sense amplifier (RS-CSA). A test-chip is silicon-verified using the 28-nm high-k/metal-gate (HKMG) logic process with foundry-developed RRAM. The test-chip performs linear analog multiply-and-accumulate (MAC) operations over 32 accumulation channels and achieves 30.34–154.04 TOPS/W with 1-bit input (IN), 3-bit weight (W), and 4-bit output (O). Evaluations with the ResNet-18 model show that the MSB-RSM scheme results in 0.96% and 2.83% improvement on CIFAR-10 and CIFAR-100 inference accuracy, respectively.

Biosensors based on field effect transistor (FET), also known as Bio‐FETs, offer numerous advantages, including high sensitivity, rapid response speed, low operating voltage, compact size, high reliability, and easily integrative. These features endow Bio‐FETs with tremendous performance in rapid analysis for samples with ultra‐low concentration at large‐scale, broadening their multiple potential applications. In recent years, the research based on Bio‐FETs has attracted more and more attention. A lot of effort is put into the challenge to improve their sensitivity, which can be influenced by various factors. This review focuses on the current approaches from multiple perspectives, including overcoming the influence of Debye shielding effects, promoting the binding efficiency of analytes and FETs surface, and improving the structures of FETs device. Correspondingly, novel strategies to increase the Debye length, facilitate high frequency electric field modulation, enhance the specific interaction efficiency, and enlarge the specific surface area (SBET) are also summarized. Additionally, there is a lack of a reliable standard method to characterize the sensitivity of FETs currently. Regarding this issue, the most commonly used definitions and representation parameters of sensitivity are also evaluated. Overall, this review outlines the potential future research directions to offer insights for enhancing the sensitivity of Bio‐FETs.

Resistive random-access memory (RRAM) based non-volatile computing-in-memory (nvCIM) has been regarded as a promising solution to enable efficient data-intensive artificial intelligence (AI) applications on resource-limited edge systems. However, existing weighted-current summation-based nvCIM suffers from device non-idealities and significant time, storage, and energy overheads when processing high-precision analog signals. To address these issues, we propose a 3T2R digital nvCIM macro for a fully hardware-implemented binary convolutional neural network (HBCNN), focusing on accelerating edge AI applications at low weight precision. By quantizing the voltage-division results of RRAMs through inverters, the 3T2R macro provides a stable rail-to-rail output without analog-to-digital converters or sensing amplifiers. Moreover, both batch normalization and sign activation are integrated on-chip. The hybrid simulation results show that the proposed 3T2R digital macro achieves an 86.2% (95.6%) accuracy on the CIFAR-10 (MNIST) dataset, corresponding to a 4.7% (1.9%) accuracy loss compared to the software baselines, which also feature a peak energy efficiency of 51.3 TOPS/W and a minimum latency of 8 ns, realizing an energy-efficient, low-latency, and robust AI processor.

Further performance improvement is necessary for resistive random access memory (RRAM) to realize its commercialization. In this work, a novel pulse operation method is proposed to improve the performance of RRAM based on Ti/HfO₂/Pt structure. In the DC voltage sweep of the RRAM device, the SET transition is abrupt under positive bias. If current sweep with positive bias is utilized in SET process, the SET switching will become gradual, so SET is current controlled. In the negative voltage sweep for RESET process, the change of current with applied voltage is gradual, so RESET is voltage controlled. Current sweep SET and voltage sweep RESET shows better controllability on the parameter variation. Considering the SET/RESET characteristics in DC sweep, in the corresponding pulse operation, the width and height of the pulse series can be adjusted to control the SET and RESET process, respectively. Our new method is different from the traditional pulse operation in which both the width and height of program/erase pulse are simply kept constant which would lead to unnecessary damage to the device. In our new method, in each program or erase operation, a series of pulses with the width/height gradually increased are made use of to fully finish the SET/RESET switching but no excessive stress is generated at the same time, so width/height-controlled accurate SET/RESET can be achieved. Through the operation, the uniformity and endurance of the RRAM device has been significantly improved.

The insufficient retention prevents the resistive random access memory from intended application, such as code storage, FPGA, encryption, and others. The retention characteristics of high resistance state (HRS) switching from different low resistance state (LRS) were investigated in a 1-kb array with one transistor and one resistor configuration. The HRS degradation was found strongly dependent on the LRS: the lower the resistance of the LRS (R_LRS) is, the worse HRS retention will be. According to the quantum point contact model, the HRS corresponds to a tiny tunnel gap or neck bridge with atomic size in the filament. The degradation of HRS is due to the filling or widening of the neck point by the diffusion of copper species from the residual filament. As the residual filament is stronger in case of the lowerR_LRS, the active area around the neck point for copper species diffusion is larger, resulting in higher diffusion probability and faster degradation of HRS during the temperature-accelerated retention measurement.

Bi-layer structure has been widely adopted to improve the reliability of the conductive bridge random access memory (CBRAM). In this work, we proposed a convenient and economical solution to achieve a Ta2O5/TaOx bi-layer structure by using a low-temperature annealing process. The addition of a TaOx layer acted as an external resistance suppressing the overflow current during set programming, thus achieving the self-compliance switching. As a result, the distributions of high-resistance states and low-resistance states are improved due to the suppression of the overset phenomenon. In addition, the LRS retention of the CBRAM is obviously enhanced due to the recovery of defects in the switching film. This work provides a simple and economical method to improve the reliability of CBRAM.