SiO₂ is one of the most widely used dielectric materials in optical and electronic devices. The Josephson voltage standard (JVS) chip fabrication process has rigorous requirements for the deposition temperature and step-coverage profiles of the SiO₂ insulation layer. In this study, we deposited high-quality SiO₂ insulation films at 60 °C using inductively coupled plasma-chemical vapor deposition (ICP-CVD) to fulfill these requirements and fabricate JVS chips simultaneously. SiO₂ films have a high density, low compressive stress, and a sloped sidewall profile over the vertical junction steps. The sidewall profiles over the vertical junction steps can be adjusted by changing the radio frequency (RF) power, ICP power, and chamber pressure. The effects of sputtering etch and sloped step coverage were enhanced when the RF power was increased. The anisotropy ratio of the deposition rate between the sidewall and the bottom of the film was lower, and the sloped step coverage effect was enhanced when the ICP power was increased, or the deposition pressure was decreased. The effects of the RF power on the stress, density, roughness, and breakdown voltage of the SiO₂ films were also investigated. Despite increased compressive stress with increasing RF power, the film stress was still low and within acceptable limits in the device. The films deposited under optimized conditions exhibited improved densities in the Fourier transform infrared spectra, buffered oxide etch rate, and breakdown voltage measurements compared with the films deposited without RF power. The roughness of the film also decreased. The step-coverage profile of the insulation layer prepared under optimized conditions was enhanced in the junction and bottom electrode regions; additionally, the performance of the device was optimized. This study holds immense significance for increasing the number of junctions in future devices.

As Nb films are widely used as superconducting electrodes of Josephson junctions, it is important to investigate the properties of Nb films in order to fabricate high-quality Josephson junctions. In this work, we conducted a comprehensive analysis of the relationships among the properties of DC magnetron sputtered Nb films with a constant power fabricated at the National Institute of Metrology (China). The film properties, including superconductivity, stress, lattice constant, and surface roughness, were investigated. It was found that in the case of constant power and Ar pressure, the stress and other parameters of the Nb films can maintain a relatively stable state during the continuous consumption of the target material.

The Nb/Al-AlO _x /Nb (SIS) Josephson junction is a crucial component in many types of superconducting devices. However, it can be easily damaged during the plasma fabrication processes. Anodic oxidation is an effective method for protecting SIS junctions by oxidizing Nb and Al from the junction profile. We used a custom wafer-scale anodic oxidation system and a neutral electrolyte to study the oxidation process of Nb films and Nb-Al(-AlO _x )-Nb junctions. The oxidation process was thoroughly characterized by considering factors such as morphology and electrical properties. Anodization spectroscopy revealed varying oxidation sections from the top Nb layer to the bottom layer, extending across the Al-AlO _x interlayer. This indicates that a 4 nm Al layer is sufficient to cover the surface of the bottom Nb film. High-resolution transmission electron microscopy and energy dispersive spectroscopy revealed that the Nb₂O₅ layer produced from the oxidation of the bottom Nb layer penetrated the Al₂O₃ layer and migrated to the top surface as the oxidation voltage increased. The top Nb layer of the SIS junction was also subjected to oxidation, despite the presence of a protective photoresist. Following the anodic oxidation process, the entire wafer surface was coated with an insulating Nb₂O₅ film. This film provided protection for the SIS junctions during the subsequent microfabrication process. The fabricated junction array, consisting of 128 junctions, demonstrated uniform electrical properties benefiting from the anodic oxidation process. This systematic analysis will further the research and practical applications of SIS junctions.

This work proposes a balanced segmentation scheme to improve microwave transmission and develops a 2 V programmable Josephson junction array using double-stacked superconductor-normal-metal-superconductor Josephson junctions. The junction numbers of the sub-Josephson arrays are divided into a ternary sequence. The least significant bit is one stack or two junctions. In order to characterize the chip with many sub-arrays, an automatic measurement system with self-made multi-channel current sources was established. It can analyze the critical current, the margin of the voltage steps, and the number of junctions in each sub-array. The measurement found that the mentioned junction arrays can work at several microwave frequency ranges with an operating margin higher than 1.5 mA. Moreover, the circuit can produce intrinsically stable DC voltages from –2 V to +2 V and generate stepwise-approximated AC voltages.

This article presents a superconducting material based planar broadband 3-way Wilkinson power divider which can be used in the Josephson quantum voltage device for the voltage standards. The 3-way Wilkinson power divider aims to improve the integration of Josephson voltage device compared to the commonly used 2-way power divider. A two-stage λ/4 section on each branch is used to increase the bandwidth, and a π model with lumped equivalent elements are used to further decrease physical dimension in device area. Different from the conventional spatial design of N-way Wilkinson power divider, this work designs a planar broadband 3-way divider to be compatible with the on-chip fabrication process. Simulation results show that the insert loss is below 0.18 dB at working bandwidth of 16.7~23 GHz, the division imbalance of each branch is below 0.044 dB, and the input and output reflection is better than 15 and 11.9 dB, respectively. The isolation between any of the three output ports is better than 11.8 dB. All these indexes satisfy the requirement of the Josephson voltage standard application. To further prove the validity of our design, real device based on superconducting material is realized and characterized. Devices with a 3-way power divider and three 2-stacked Josephson junction arrays with 256 junctions in each array are fabricated. The experiment results indicate the potential usage of our design in quantum voltage standard devices for high-voltage output.