SiO₂ is one of the most widely used dielectric materials in optical and electronic devices. The Josephson voltage standard (JVS) chip fabrication process has rigorous requirements for the deposition temperature and step-coverage profiles of the SiO₂ insulation layer. In this study, we deposited high-quality SiO₂ insulation films at 60 °C using inductively coupled plasma-chemical vapor deposition (ICP-CVD) to fulfill these requirements and fabricate JVS chips simultaneously. SiO₂ films have a high density, low compressive stress, and a sloped sidewall profile over the vertical junction steps. The sidewall profiles over the vertical junction steps can be adjusted by changing the radio frequency (RF) power, ICP power, and chamber pressure. The effects of sputtering etch and sloped step coverage were enhanced when the RF power was increased. The anisotropy ratio of the deposition rate between the sidewall and the bottom of the film was lower, and the sloped step coverage effect was enhanced when the ICP power was increased, or the deposition pressure was decreased. The effects of the RF power on the stress, density, roughness, and breakdown voltage of the SiO₂ films were also investigated. Despite increased compressive stress with increasing RF power, the film stress was still low and within acceptable limits in the device. The films deposited under optimized conditions exhibited improved densities in the Fourier transform infrared spectra, buffered oxide etch rate, and breakdown voltage measurements compared with the films deposited without RF power. The roughness of the film also decreased. The step-coverage profile of the insulation layer prepared under optimized conditions was enhanced in the junction and bottom electrode regions; additionally, the performance of the device was optimized. This study holds immense significance for increasing the number of junctions in future devices.

This work proposes a balanced segmentation scheme to improve microwave transmission and develops a 2 V programmable Josephson junction array using double-stacked superconductor-normal-metal-superconductor Josephson junctions. The junction numbers of the sub-Josephson arrays are divided into a ternary sequence. The least significant bit is one stack or two junctions. In order to characterize the chip with many sub-arrays, an automatic measurement system with self-made multi-channel current sources was established. It can analyze the critical current, the margin of the voltage steps, and the number of junctions in each sub-array. The measurement found that the mentioned junction arrays can work at several microwave frequency ranges with an operating margin higher than 1.5 mA. Moreover, the circuit can produce intrinsically stable DC voltages from –2 V to +2 V and generate stepwise-approximated AC voltages.

Transition-edge sensors (TESs) have shown remarkable energy resolution and photon-number resolving ability. In this paper, we report the fabrication and characterization of Ti/Au optical TESs for the detection of single photon at the telecommunication wavelength 1550 nm. A SiO ₂ /SiN _x antireflection coating is deposited on top of TESs by an inductively coupled plasma-assisted plasma-enhanced chemical vapor deposition (ICP-PECVD) process to improve the detection efficiency. Ti/Au (50/60 nm) TES with a small sensitive area 10 µm× 10 µm shows an energy resolution of 0.12 eV. The TES with a large sensitive area 20 µm× 20 µm can discriminate up to 55 incident photons and the detection efficiency is 46%.