The quantum point contact (QPC) model for dielectric breakdown is used to explain the electron transport mechanism in HfO₂-based resistive random access memories (ReRAM) with TiN(30 nm)\HfO₂(5 nm)\Hf(10 nm)\TiN(30 nm) stacks. Based on experimental I-V characteristics of bipolar HfO₂-based ReRAM, we extracted QPC model parameters related to the conduction mechanism in several devices in order to make a statistical study. In addition, we investigated the temperature effect on the conduction mechanism and compared it with the QPC model. Based on these experimental results, we show that the QPC model agrees well with the conduction behavior of HfO₂-based ReRAM memory cells.

This paper focuses on the time-dependent breakdown of the AlGaN/GaN Schottky barrier diodes with a gated edge termination (GET) submitted to high-voltage stress. The impact of the GET structure, the passivation layer thickness, and a preclean process (sulfuric acid and hydrogen peroxide mixture + ammonia and hydrogen peroxide mixture) before the GET layer deposition on the time to breakdown t _BD is analyzed. Initially, a reference structure with a single-GET structure, a thick passivation layer and excellent performance under dc, and pulse characterization is submitted to stress. The results show that the time to failure follows a Weibull distribution with high shape parameter values (β ~ 3 and/or β ~ 5) related to intrinsic failure mechanisms. The exponential dependence of tBD on the stress voltage suggests a degradation driven by the electric field, while lower thermal activation energies indicate that temperature acts as a weak acceleration factor. A more uniform distribution of the electric field-by adding an additional peak (double-GET structure) or with more equilibrated peaks (thin passivation structure)-and a more aggressive preclean process before the GET layer deposition improves the breakdown voltage and prolongs the device lifetime.

The authors demonstrate high-performing n-channel transistors with a HfO₂/TaN gate stack and a low thermal-budget process using solid-phase epitaxial regrowth of the source and drain junctions. The thinnest devices have an equivalent oxide thickness (EOT) of 8 Aring, a leakage current of 1.5 A/cm² at V_G=1 V, a peak mobility of 190 cm²/Vmiddots, and a drive-current of 815 muA/mum at an off-state current of 0.1 muA/mum for V_DD=1.2 V. Identical gate stacks processed with a 1000-degC spike anneal have a higher peak mobility at 275 cm²/Vmiddots, but a 5-Aring higher EOT and a reduced drive current at 610 muA/mum. The observed performance improvement for the low thermal-budget devices is shown to be mostly related to the lower EOT. The time-to-breakdown measurements indicate a maximum operating voltage of 1.6 V (1.2 V at 125 degC) for a ten-year lifetime, whereas positive-bias temperature-instability measurements indicate a sufficient lifetime for operating voltages below 0.75 V

Channel hot carrier (CHC) stress is observed to result in higher variability of degradation in deeply-scaled nFinFETs than bias temperature instability (BTI) stress. Potential sources of this increased variation are discussed and the intrinsic time-dependent variability component is extracted using a novel methodology based on matched pairs. It is concluded that in deeply-scaled devices, CHC-induced time-dependent distributions will be bimodal, pertaining to bulk charging and to interface defect generation, respectively. The latter, high-impact mode will control circuit failure fractions at high percentiles.