As an atomically thin semiconductor, 2D molybdenum disulfide (MoS₂) has demonstrated great potential in realizing next-generation logic circuits, radio-frequency (RF) devices and flexible electronics. Although various methods have been performed to improve the high-frequency characteristics of MoS₂ RF transistors, the impact of the back-gate bias on dual-gate MoS₂ RF transistors is still unexplored. In this work, we study the effect of back-gate control on the static and RF performance metrics of MoS₂ high-frequency transistors. By using high-quality chemical vapor deposited bilayer MoS₂ as channel material, high-performance top-gate transistors with on/off ratio of 10⁷ and on-current up to 179 μA/μm at room temperature were realized. With the back-gate modulation, the source and drain contact resistances decrease to 1.99 kΩ∙μm at V_bg = 3 V, and the corresponding on-current increases to 278 μA/μm. Furthermore, both cut-off frequency and maximum oscillation frequency improves as the back-gate voltage increases to 3 V. In addition, a maximum intrinsic f_max of 29.7 GHz was achieved, which is as high as 2.1 times the f_max without the back-gate bias. This work provides significant insights into the influence of back-gate voltage on MoS₂ RF transistors and presents the potential of dual-gate MoS₂ RF transistors for future high-frequency applications.

A low-power SAR ADC with capacitor-splitting energy-efficient switching scheme is proposed for wearable biosensor applications. Based on capacitor-splitting, additional reference voltage V_cm, and common-mode techniques, the proposed switching scheme achieves 93.76% less switching energy compared to the conventional scheme with common-mode voltage shift in one LSB. With the switching scheme, the proposed SAR ADC can lower the dependency on the accuracy of V_cm and the complexity of digital control logic and DAC driver circuits. Furthermore, the SAR ADC employs low-noise and low-power dynamic comparators utilizing multi-clock control, low sampling error sampling switches based on the bootstrap technique, and dynamic SAR logic. The simulation results demonstrate that the ADC achieves a 61.77 dB SNDR and a 78.06 dB SFDR and consumes 4.45 μW of power in a 180 nm process with a 1 V power supply, a full-swing input signal frequency of 93.33 kHz, and a sampling rate of 200 kS/s.

An energy-efficient, area-efficient, high-accuracy and low-complexity switching scheme for successive approximation register (SAR) analogue-to-digital converter (ADC) is proposed. In the proposed switching scheme, both the first and the second comparisons don’t consume switching energy, and all the rest of comparisons consume little switching energy. As a result, the proposed switching scheme achieves a 95.34% switching energy reduction and a 75% area reduction compared with the conventional method. In addition, only the least significant bit (LSB) is depended on the accuracy of V_cm. Moreover, only two reference voltages are used for each capacitor, which lowers complexity of digital control logic.

The shortage of color in traditional electrophoretic displays (EPDs) can be compensated by three-color EPDs. However, the response time of black particles and white particles is increased. A new driving waveform based on the principle of three-color EPDs and electrophoresis theory was proposed to shorten the response time of black particles and white particles. The proposed driving waveform consisted of an erasing stage, an activation stage, a red driving stage, and a white or a black driving stage. The activation stage was mainly optimized in this paper. Firstly, the motion characteristics of the particles were analyzed using Stokes law and electrophoresis theory. Secondly, an optimal high frequency oscillation voltage was tested in order to improve the activity of the particles. Then, the influence of oscillation period and oscillation times on the activation stage were analyzed for optimizing the reference grayscale. According to the luminance of pixels, an oscillation period of 30 ms and an oscillation time of 30 were determined. The experimental results showed that the response time of black particles was shortened by 45%, and the response time of white particles was shortened by 40% compared with a traditional driving waveform.

A DAC switching scheme that combines energy efficiency and resolution reconfigurability is proposed. Compared with the conventional switching scheme, the proposed scheme achieves 93.8%, 96.1%, and 97.3% switching energy saving in 8-bit, 9-bit, and 10-bit modes, respectively. Based on the proposed switching scheme, an 8–10-bit resolution-reconfigurable SAR ADC for biosensor applications is designed. The ADC consists of resolution-reconfigurable binary-weighted capacitive DAC, a two-stage full dynamic comparator, sampling switch, and the resolution-control SAR logic. Simulated in 180 nm CMOS process and 100 kS/s sampling rate, the ADC achieves the 46.80/53.89/60.14 dB signal-to-noise and distortion ratio (SNDR), the 55.22/62.51/73.09 dB spurious-free dynamic range (SFDR) and the 0.81/0.91/1.01 μW power consumption in 8/9/10-bit mode, respectively.

A hybrid energy-efficient, area-efficient, low-complexity switching scheme in SAR ADC for biosensor applications is proposed. This scheme is a combination of the monotonic technique, the MSB capacitor-splitting technique, and a new switching method. The MSB capacitor-splitting technique, as well as the reference voltage V_aq allow for more options for reference voltage conversion, resulting in higher area savings and higher energy efficiency. In a capacitor array, the circuit performs unilateral switching during all comparisons except for the second and last two comparisons, reducing the difficulty in designing the drive circuit. The proposed switching scheme saves 98.4% of the switching energy and reduces the number of unit capacitors by 87.5% compared to a conventional scheme. Furthermore, the SAR ADC employs low-noise and low-power dynamic comparators utilizing multi-clock control, low-sampling error-sampling switches based on the bootstrap technique, and dynamic SAR logic. The simulation results demonstrated that the proposed SAR ADC achieves 61.51 dB SNDR, 79.21 dB SFDR and consumes 0.278 μW of power in a 180 nm process with a 1 V power supply, a full swing input signal frequency of 23.33 kHz, and a sampling rate of 100 kS/s.