Power cycling test (PCT) is an effective method to evaluate the SiC mosfet s' long-term reliability, including lifetime and degradation mechanisms. Some of the aging precursors of PCT have been identified in the previous literature. But when multiple failure mechanisms compete with each other, the individual precursors are nullified. Although PCT is mainly used to evaluate the package reliability, there are still unresolved problems due to the gate oxide reliability of SiC mosfet , and the repeated gate stress of the power cycling has different effects on the devices with different gate structures. This article presents a comprehensive investigation of the aging precursors and failure mechanism of three typical commercial SiC mosfet s with different gate structures through PCTs under two different conduction modes. Degradation-related essential precursors and possible causes behind them are discussed. The failure mechanisms and correlation with the degradation state of different devices are studied in depth. In addition, the effects of PCT under different conduction modes on failure mechanism and lifetime have been investigated.

Aluminum electrolytic capacitors (AEC) are widely used in switching mode power supply (SMPS) as smoothing capacitor, but they are the weakest among power components in DC-DC converter. It is very important to monitor its electrical parameters, mainly the equivalent series resistance (ESR). A monitoring method of capacitor's ESR for buck converters is proposed in this paper. Based on the calculation model of ESR, the target parameter is monitored by sampling output ripple voltage. The proposed method needs no current sensor. Whether the circuit is in continuous conduction mode (CCM) or discontinuous conduction mode (DCM), it is convenient to monitor the capacitor. Implementation of the monitoring system is presented. The experimental results validate the effectiveness of the method.

This article presents a frontend amplifier based on the 50- $\mu \text{m}$ channel length n-type only indium–tin-oxide (ITO)-stabilized ZnO thin-film transistors (TFTs) on glass substrate. The amplifier has an external-bias ac-coupled, open-loop capacitor bootstrap structure. The area and power consumption are 41 mm ² and 0.1 mW (8-V supply), respectively. Electrical measurement results show a gain of 20 dB, a bandwidth of 3 Hz–6 kHz, a common-mode rejection ratio (CMRR) up to 42 dB, an input impedance of 100 $\text{M}\Omega $ , and an input-referred noise of $106 ~\mu \text{V}_{rms}$ (integrated from 1 to 200 Hz). The noise efficiency factor (NEF) and power efficiency factor (PEF) of the amplifier are, respectively, 248 and $4.9\times10$ ⁵ , which is comparable among the state of the arts. The amplifier is successfully used to measure the heart-rate signal, which demonstrates its practicality.

This article proposes a low-power differential logic (DL) row/column decoder for radio frequency identification (RFID) code generators, which is used to optimize the power consumption of RFID at the circuit level. In addition, a pull-up control ring oscillator (PUC-RO) is also applied to further power optimization. For comparison, we fabricate three kinds of code generators with unipolar metal-oxide thin-film transistors (MO TFTs) using an indium tin oxide (ITO)-stabilized ZnO active channel layer. The power consumption of the code generator with a DL decoder is reduced by more than 20% under the same supply voltage compared to the conventional pseudo-CMOS design. The power consumption of the code generator with a DL decoder and PUC-RO is reduced by more than 40%. These results reveal a new perspective for power optimization of RFID tags based on TFTs technology.

In this paper, a high gain amplifier with phase compensation loop is presented. A structure of parallel gate cross-coupled transistors to both ends of differential pair drain and source is designed to improves the load impedance, which obtains sufficient gain and further reduces power consumption. A novel capacitor bootstrap load circuit is proposed. The capacitor bootstrap topology is constructed by the drain source resistance of the transistor working in the cut-off region, where the gate source parasitic capacitor of the transistor is in parallel with the bootstrap capacitor rather than the existing series structure, thereby only a small bootstrap capacitor is required. By avoiding the use of large capacitors, chip area can be effectively reduced without compromising performance such as gain and bandwidth. The amplifier is fabricated using 10-μm n-type a-IGZO TFT technology. Measurement results show that the proposed amplifier achieves a voltage gain of 43.5dB and a common mode rejection ratio of 61.2dB while maintaining low power consumption. The amplifier also exhibits a -3dB bandwidth covering 0.4~2.1KHz, encompassing major bioelectric frequency bands. A real-time ECG signal was successfully captured using the fabricated TFT amplifier and gel electrodes. It has great potential in flexible sensing and acquisition applications such as electro cardiogram (ECG), electro encephalogram (EEG), pulse detection, and other wearable applications.