Alessandro Parisi

Dr. Alessandro Parisi

orcid

Research Focus & Metrics

Academic Career Length

9Years (2018-Present)

(Calculated once Scilit publication data is synced: current year − year of first publication + 1)

Representative Publications

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15 May 2021 in Electronics
Verified
Journal Article
Open access
PDF file
Egidio RagoneseEgidio Ragonese
Egidio Ragonese
NSNunzio Spina
Nunzio Spina
APAlessandro Parisi
Alessandro Parisi
GPGiuseppe Palmisano
Giuseppe Palmisano
This paper reviews state-of-the-art approaches for galvanically isolated DC-DC converters based on radio frequency (RF) micro-transformer coupling. Isolation technology, integration level and fabrication issues are analyzed to highlight the pros and cons of fully integrated (i.e., two chips) and multichip systems-in-package (SiP) implementations. Specifically, two different basic isolation technologies are compared, which exploit thick-oxide integrated and polyimide standalone transformers, respectively. To this aim, previously available results achieved on a fully integrated isolation technology (i.e., thick-oxide integrated transformer) are compared with the experimental performance of a DC-DC converter for 20-V gate driver applications, specifically designed and implemented by exploiting a stand-alone polyimide transformer. The comparison highlights that similar performance in terms of power efficiency can be achieved at lower output power levels (i.e., about 200 mW), while the fully integrated approach is more effective at higher power levels with a better power density. On the other hand, the stand-alone polyimide transformer approach allows higher technology flexibility for the active circuitry while being less expensive and suitable for reinforced isolation.

4 May 2021 in IEEE Transactions on Microwave Theory and Techniques
Verified
Journal Article
Closed access
GPGiuseppe Papotto
Giuseppe Papotto
CNClaudio Nocera
Claudio Nocera
AFAlessandro Finocchiaro
Alessandro Finocchiaro
APAlessandro Parisi
Alessandro Parisi
ACAndrea Cavarra
Andrea Cavarra
GPGiuseppe Palmisano
Giuseppe Palmisano
This paper presents a 77-GHz automotive radar receiver in a 28-nm fully depleted silicon-on-insulator CMOS technology. It exploits a mixer-first direct-conversion architecture to trade-off noise and linearity performance. The receiver is composed of a 77-GHz downconverter, a variable-gain amplifier, and a switched-capacitor low-pass filter. It adopts an effective and robust approach for leakage suppression due to the TX to RX crosstalk, which overcomes both gain and linearity limitations. The receiver draws an overall quiescent current as low as 27 mA from a 1-V supply voltage and provides an overall gain up to 75 dB with a noise figure of 8.2 dB. Despite the low supply voltage, an excellent blocker immunity of -9.5 dBm is achieved along with an output 1-dB compression point as high as -1.5 dBV.

25 July 2018 in IEEE Transactions on Circuits and Systems II: Express Briefs
Verified
Journal Article
Closed access
APAlessandro Parisi
Alessandro Parisi
AFAlessandro Finocchiaro
Alessandro Finocchiaro
GPGiuseppe Papotto
Giuseppe Papotto
GPGiuseppe Palmisano
Giuseppe Palmisano
This brief presents a fully CMOS voltage reference based on a self-biased topology, which provides low current consumption while saving silicon area. Temperature compensation is achieved by means of a subthreshold triode-based Widlar current reference and a proper arrangement of an active load. The proposed voltage reference was fabricated in a standard 0.13-μm CMOS technology and occupies a core area as low as 0.003 mm 2 . The circuit properly operates with a power supply ranging from 2.4 V to 1.1 V while providing a reference voltage of around 800 mV with an average temperature coefficient of 100 ppm/°C and an overall current consumption below 25 nA. This performance makes the proposed voltage reference very suitable for RF-powered applications.

15 July 2020 in IEEE Transactions on Circuits and Systems I: Regular Papers
Verified
Journal Article
Closed access
APAlessandro Parisi
Alessandro Parisi
Egidio RagoneseEgidio Ragonese
Egidio Ragonese
NSNunzio Spina
Nunzio Spina
GPGiuseppe Palmisano
Giuseppe Palmisano
This paper presents a galvanically isolated dc-dc converter with multi-channel communication exploiting a single isolation transformer. The proposed architecture makes compliant both regulated output power and data transmission on the same isolation physical link by using ASK modulation of the power signal and data/control signal multiplexing. The dc-dc converter consists of two integrated chips fabricated in 0.18-μm BCD and 0.13-μm CMOS technologies, respectively, along with a thick polyimide transformer chip able to comply with reinforced isolation requirements. The dc-dc converter delivers an isolated output power up to 50 mW at 3.3-V output voltage, while providing three data channels with a data rate up to 10 Mb/s.

7 June 2018 in IEEE Transactions on Circuits and Systems I: Regular Papers
Verified
Journal Article
Closed access
NGNunzio Greco
Nunzio Greco
APAlessandro Parisi
Alessandro Parisi
PLPierpaolo Lombardo
Pierpaolo Lombardo
NSNunzio Spina
Nunzio Spina
Egidio RagoneseEgidio Ragonese
Egidio Ragonese
GPGiuseppe Palmisano
Giuseppe Palmisano
This paper presents a double-isolated dc-dc converter exploiting integrated LC galvanic barriers. The converter consists of only two dice both fabricated in a 0.35-μm BCD technology with a thick-oxide back-end for 5-kV galvanic isolation. It uses a novel architecture to transmit power and the control feedback signal across two double isolation barriers, which are performed by integrated isolation capacitors and transformers. A resonant mode operation for the isolation networks is exploited to boost efficiency with respect to traditional converter schemes based on series-connected isolation components. Measurements of the dc-dc converter at 3.3-V power supply demonstrate 100-mW dc output power with a power efficiency of 16.8% at a regulated output voltage of 3.3 V.

5 June 2020 in Electronics
Verified
Journal Article
Open access
PDF file
Egidio RagoneseEgidio Ragonese
Egidio Ragonese
NSNunzio Spina
Nunzio Spina
APAlessandro Parisi
Alessandro Parisi
GPGiuseppe Palmisano
Giuseppe Palmisano
This paper exploits an effective approach to overcome the breakdown limitations of traditional galvanic isolators based on chip-scale isolation barriers, thus achieving a very high isolation rating (i.e., compliant with the reinforced isolation requirements). Such an approach is based on radio frequency (RF) planar coupling between two side-by-side co-packaged chips. Standard packaging along with proper assembling techniques can be profitably used to go beyond 20-kV surge voltage without using expensive or exotic isolation components. As a proof of concept, a bidirectional data transfer system based on RF planar coupling able to withstand an isolation rating as high as 25 kV has been designed in a low-cost standard 0.35-µm CMOS technology. Experimental measurements demonstrated a maximum data rate of 40 Mbit/s using a carrier frequency of about 1 GHz. The adopted approach also guarantees a common mode transient immunity (CMTI) of 250 kV/µs, which is a first-rate performance in view of next generation galvanic isolators for wide-bandgap power semiconductor devices, such as gallium nitride high-electron mobility transistors (GaN HEMTs) and silicon carbide (SiC) MOSFETs.