The ${I}$ – ${V}$ characteristics of 4H-SiC N/P-channel MOSFETs have been carried out at high temperatures up to 300 °C. Different scattering mechanisms of surface mobility for 4H-SiC N-channel MOSFETs have been studied in this article. Moreover, the temperature dependencies of various scattering mobilities for P-channel MOSFETs are given for the first time. Their temperature dependencies were simulated and analyzed at a temperature ranging from 27 °C to 300 °C. Furthermore, an improved method of extracting trapped charge from transfer characteristic is proposed, such that the density of occupied interface traps in a strong inversion can be extracted. The analysis of experimental results shows that sacrificial oxidation can decrease the occupied interface traps at high temperatures but not much effective at room temperature, and the Coulomb scattering in 4H-SiC P-channel MOSFETs has always been the main mechanism from 27 °C to 300 °C, which is different from 4H-SiC N-channel MOSFETs.

Recent research has revealed that SiC power MOSFETs can experience failures at remarkably low gate stress after heavy ion irradiation, even though no discernible degradation in gate leakage current can be measured during irradiation. However, the damage structure has yet to be precisely analyzed. In this article, the nanoscale structure and element distribution of the degradation site in gate leakage current failure devices after post-irradiation gate stress (PIGS) tests were investigated. A gate leakage current failure occurred in PIGS tests of a 1200 V SiC power MOSFET with only 50 V drain bias during irradiation. Further failure analysis using transmission electron microscope (TEM) and energy dispersive X-ray (EDX) revealed a 50-nm wide structural defect in the gate oxide layer directly above the JFET region, which was mainly filled with polysilicon. Suspected latent damage was also observed adjacent to the damaged region. Besides the gate oxide damage, defects were observed on the SiC surface and the polysilicon gate. Through the internal physical response simulation, the picosecond short response time of the electric field in the gate oxide layer can be highly destructive and a critical factor contributing to potential failures at lower drain bias. The diffusion of holes on SiC surfaces causes an extension of the degradation region where the electric field changes.

The threshold voltage ( ${V}_{\text {th}}$ ) instability induced by gate stress has always been a significant reliability issue for silicon carbide (SiC) MOSFET. The negative bias temperature instability (NBTI) of 4H-SiC p-channel MOSFET (pMOS) was studied experimentally at 200 °C and compared with that of 4H-SiC n-channel MOSFET (nMOS). It is shown that the ${V}_{\text {th}}$ drift of pMOS after 20 ks of negative stress −18 or −30 V is around twice that of nMOS. The behavior of the interface traps after stress is also analyzed quantitatively. It is concluded that the hole oxide traps are the dominant mechanism resulting in this large ${V}_{\text {th}}$ drift difference between pMOS and nMOS, and the interface traps have little contribution to the threshold voltage drift in this study. Moreover, in a double logarithmic plot, the ${V}_{\text {th}}$ recovery curves at a gate voltage of 0 V indicate that nMOS has a faster recovery than pMOS at the initial time. And the slope of ${V}_{\text {th}}$ recovery curve for pMOS becomes larger after 100 s.

In this article, a new online temperature measurement method for silicon carbide power metal–oxide–semiconductor field-effect transistors ( mosfet s) is proposed that uses the linear relationship between the drain–source current ( I_ds ) and the temperature of power electronic devices. The temperature-sensitive characteristics of the transfer characteristic curve of these mosfet s are studied. The results show that, under different applied gate voltages, the effects of temperature on the change in the I_ds are different; under the same gate voltage, the drain–source current of each device maintains a good linear relationship with the temperature, which can be used to perform the accurate junction temperature measurements of power mosfet s. Based on this characteristic, by superimposing a pulse on the gate, characterizing the instantaneous current produced by this superimposed pulse, and combining this characteristic with the relationship between the I_ds change and temperature, detection of the device's operating temperature under actual working conditions is realized. Furthermore, a related circuit is designed to reduce the influence of changes in the electrical bias on the system stability during temperature measurements. In addition, the measurement results are verified via infrared thermal imaging, and the results show that the proposed method has good practicability.

Leakage current of 1200 V 4H-SiC Schottky Barrier diodes (SBDs) with different structures increased by various degrees after heavy-ion exposure. By taking I-V measurements in a range of 298 to 448 K, the voltage dependence of saturation current (I0), barrier height (ϕB0), and ideality factor (n) were obtained. The dependence of these parameters with temperature illustrates the Gaussian distribution of barrier height. The inhomogeneity of the Schottky barrier height distribution was successfully described using a modified thermionic emission model with Gaussian distribution, and the average barrier height (¯ϕB0) was gained. The results show that the barrier height distribution of all SBDs remain unchanged after the irradiation which means heavy-ion exposure did not affect the Schottky barrier.

The gate oxide instability of 4H-SiC pMOS induced by ac stress was experimentally investigated at 200 $^\circ$ C for the first time. The threshold voltage drift ( $\Delta \textit{V}_{\text{th}}$ ) of pMOS under different stress conditions was experimentally measured. The results show that high-frequency ac stress could cause the additional $\Delta \textit{V}_{\text{th}}$ . Furthermore, it was found first that high-frequency ac stress will cause the gate oxide breakdown at 200 $^\circ$ C. However, no gate oxide breakdown was found at 27 $^\circ$ C. By investigating the effects of ac stress conditions on the gate oxide breakdown, it is demonstrated that the captured electrons in interface states at low-level voltage (inversion) play an important role in the gate oxide breakdown.