Gallium nitride (GaN)-based vertical power Schottky barrier diode (SBD) has demonstrated outstanding features in high-frequency and high-power applications. This paper reviews recent progress on GaN-based vertical power SBDs, including the following sections. First, the benchmark for GaN vertical SBDs with different substrates (Si, sapphire, and GaN) are presented. Then, the latest progress in the edge terminal techniques are discussed. Finally, a typical fabrication flow of vertical GaN SBDs is also illustrated briefly.

In this article, the single-event response of the 1.2-kV silicon-carbide (SiC) power MOSFETs with varied buffer layer designs is investigated by the 2-D numerical simulations. The structural parameters of the buffer layers are compared and analyzed to understand the transient response after the heavy ion strike and the related physical mechanisms comprehensively. Simulation results reveal that an optimized single buffer structure can be acquired by using a relatively thicker buffer layer (T μm) and a moderate doping concentration (D cm⁻³). It demonstrates that the single-event-burnout (SEB) performance can be improved significantly under the worst case bias conditions [a drain bias voltage of 1.2 kV and a linear energy transfer (LET) of 1 pC/μm]. In addition, the optimized structural combinations adopted in the dual or triple buffer layers can strengthen the SEB performance further. The simulation results show that a step electric field distribution is established inside the optimized dual or triple buffers, where the electric field peak is mitigated from 3 to 2.2 MV/cm. Moreover, the excess carrier generation is suppressed and the local temperature rise is weakened during the transient electrothermal process. Consequently, the structure with the optimal buffer layer designs can enlarge the SEB safe operating area (SOA) from 30%-50% to 100% rated breakdown voltage at high LET bias, which makes the SiC power MOSFETs used in aerospace and aviation power electronic systems become possible.

SiC MOSFET integrated with Schottky barrier diode (SBD) can handle the reverse current during switching operation and reduce the package cost. However, the integrated SBD weakens the high-voltage-withstanding capability of the SiC MOSFET. In this article, a novel 4H-SiC trench MOSFET integrated with mesa-sidewall SBD (TMS-SBD) is proposed and studied with the 2-D simulation. Compared with the trench MOSFET integrated with the SBD locating on the mesa (TM-SBD), the TMS-SBD shows a larger breakdown voltage (BV), a lower electric field in the gate oxide, and a better tradeoff between BV and specific ON-resistance. The TMS-SBD also shows the same current capability as that of the TM-SBD. Due to the removal of one sidewall overlap between the gate electrode and drain electrode, the reverse capacitance of TMS-SBD is lower than that of the TM-SBD. In double-pulse test simulation, the turn-on loss and turn-off loss of the TMS-SBD reduce by 30% and 56% than those of the TM-SBD, respectively. Therefore, the TMS-SBD is a more attractive device in high-voltage, high-reliability, and low-switching-loss applications.

The ${I}$ – ${V}$ characteristics of 4H-SiC N/P-channel MOSFETs have been carried out at high temperatures up to 300 °C. Different scattering mechanisms of surface mobility for 4H-SiC N-channel MOSFETs have been studied in this article. Moreover, the temperature dependencies of various scattering mobilities for P-channel MOSFETs are given for the first time. Their temperature dependencies were simulated and analyzed at a temperature ranging from 27 °C to 300 °C. Furthermore, an improved method of extracting trapped charge from transfer characteristic is proposed, such that the density of occupied interface traps in a strong inversion can be extracted. The analysis of experimental results shows that sacrificial oxidation can decrease the occupied interface traps at high temperatures but not much effective at room temperature, and the Coulomb scattering in 4H-SiC P-channel MOSFETs has always been the main mechanism from 27 °C to 300 °C, which is different from 4H-SiC N-channel MOSFETs.

The threshold voltage ( ${V}_{\text {th}}$ ) instability induced by gate stress has always been a significant reliability issue for silicon carbide (SiC) MOSFET. The negative bias temperature instability (NBTI) of 4H-SiC p-channel MOSFET (pMOS) was studied experimentally at 200 °C and compared with that of 4H-SiC n-channel MOSFET (nMOS). It is shown that the ${V}_{\text {th}}$ drift of pMOS after 20 ks of negative stress −18 or −30 V is around twice that of nMOS. The behavior of the interface traps after stress is also analyzed quantitatively. It is concluded that the hole oxide traps are the dominant mechanism resulting in this large ${V}_{\text {th}}$ drift difference between pMOS and nMOS, and the interface traps have little contribution to the threshold voltage drift in this study. Moreover, in a double logarithmic plot, the ${V}_{\text {th}}$ recovery curves at a gate voltage of 0 V indicate that nMOS has a faster recovery than pMOS at the initial time. And the slope of ${V}_{\text {th}}$ recovery curve for pMOS becomes larger after 100 s.

In this paper, with Sentaurus TCAD simulation, the trench/planar MOSFET (TPMOS) shows a much lower electric field in gate oxide and a smaller gate charge than the traditional trench MOSFET (TMOS) and commercial double trench MOSFET (DTMOS). Besides, compared with DTMOS, the TPMOS also has a smaller specific on-resistance. These advantages make the TPMOS more suitable for being integrated with a Schottky barrier diode (SBD) to reduce both conduction loss and switching loss. Therefore, the trench/planar 4 H-SiC MOSFET integrated with SBD (TPSBD) is firstly proposed and studied. For the TPSBD, the static simulation results show that the maximum reverse current without the body diode turning on is 1320 A cm ⁻² in the third quadrant. In the double pulse test with a load current of 1000 A cm ⁻² , the body diode of the TPSBD is successfully suppressed. However, the body diodes of the other three MOSFETs turn on and contribute 75% of the freewheeling currents, even though an external SBD is anti-parallel with these MOSFETs. The body diodes still contribute 25% of the freewheeling currents, even though the active area of the anti-parallel SBD increases three times. Compared with TMOS, DTMOS and TPMOS, the reverse recovery charge of the TPSBD reduces by 91%, 88% and 96%, respectively. The total switching loss of the TPSBD also reduces by 83%, 71% and 66% in contrast with TMOS, DTMOS and TPMOS, respectively. Therefore, the TPSBD is a superior choice for low reverse recovery charge and low switching loss application.