A p-type shield region (p-shield) under the gate trench is typically adopted in a SiC trench MOSFET for achieving a lower oxide field and reverse transfer capacitance ( ${C}_{rss})$ . This paper comparatively studies the effects of a grounded p-shield and a floating p-shield. Device simulations using Sentaurus TCAD are carried out in this paper to reveal the devices’ internal dynamics. The floating p-shield can effectively reduce the OFF-state oxide field as a grounded p-shield does, without degrading its static performance. However, after being switched from the OFF-state, the ON-state oxide field in the trench MOSFET with a floating p-shield (FS-MOS) is dramatically elevated. Compared with the trench MOSFET with a grounded p-shield, the FS-MOS also exhibits a higher ${C}_{{{\text {rss}}}}$ and a consequently slower switching speed. Furthermore, the FS-MOS exhibits a degradation of dynamic ${R}_{{ \mathrm{ON}}}$ during switching operation. A charge storage mechanism is then presented to explain the dynamics in FS-MOS. Upon a high ${V}_{{{\text {DS}}}}$ , holes are emitted from the floating p-shield when the parasitic p-n-p structure consisting of p-shield, p-body, and n-region between them is punched through, leaving negative charges in the floating p-shield even when the high ${V}_{{{\text {DS}}}}$ is removed. Based on this mechanism, the behaviors of the FS-MOS are well explained.

We propose a SiC trench/planar MOSFET (TP-MOS) which features a trench channel and a planar channel in one half-cell. Numerical simulations with Sentaurus TCAD have been carried out to study the proposed device architecture. Compared with traditional planar MOSFET (P-MOS), the TP-MOS has a much lower RON owing to the increased channel density. Unlike traditional trench MOSFET (T-MOS) which enables a higher channel density at the price of a high bottom-oxide field in the high-voltage OFF-state, the TP-MOS features bottom p-bases as in the P-MOS that protect the gate oxide from high electric field. The OFF-state oxide field in the TP-MOS is found to be even lower than the P-MOS. In addition, the TP-MOS boasts a low feedback capacitance (C _rss ) and gateto-drain charge (Q _GD ), since the coupling between the gate and the drain is suppressed by the collective effects of the top p-bases and the bottom p-bases. The Q _G of the TP-MOS is nearly the same as the P-MOS, and is much smaller than the T-MOS. Superior figures of merit (Q _G ×R _ON and Q _GD ×R _ON ) are achieved in the TP-MOS.

Developing E-mode p-channel field-effect transistors (p-FETs) on the standard p-GaN gate HEMT epi-wafer is highly motivated to facilitate the realization of gallium nitride (GaN) complementary logic (CL) circuits and power-integrated circuits (PICs). The gate etching process is commonly employed in the fabrication of E-mode GaN p-FETs. However, due to gate etching-induced damage, the performance of E-mode GaN p-FETs often fails to meet expectations. To address the above issue, a post-etch wet treatment technique was developed in this work to enhance the performance of E-mode GaN p-FETs. The fabricated GaN p-FET with $\textit{L}_{\text{G}}$ $=$ 2 $\mu$ m exhibits an E-mode operation with $\textit{V}_{\text{th}}$ $=$ $-$ 2.9 V. The p-FET with post-etch wet treatment exhibits a current density of 5.4 mA/mm. Compared to the p-FET without wet treatment (1.9 mA/mm), the current density has increased by more than double. Atomic force microscopy (AFM) was utilized to characterize the surface morphology and validate the effectiveness of post-etch wet treatment. To suppress the leakage current, multienergy fluorine ion implantation was implemented for planar isolation of GaN p-FETs, high $\textit{I}_{\text{ON}}$ / $\textit{I}_{\text{OFF}}$ with over 6 $\times$ 10 $^{\text{5}}$ was obtained.

A systematic analytical investigation of the charge distribution and gate control of the normally-off GaN double-channel MOS-HEMT (DC-MOS-HEMT) is presented in this paper. Compared to conventional GaN MOS-HEMT, the DC-MOS-HEMT features a thin AlN insertion layer (AlN-ISL) below the original two dimensional electron gas (2DEG) channel, thus forming a second channel at the interface between AlN-ISL and the underlying GaN. This paper reveals the impact of the AlN-ISL on the 2DEG distribution and the gate control of the channels. The sensitivity of ${V}_{\text {th}}$ against the recess depth is also analytically studied and is found to be nearly independent of the recess depth as long as the recess is terminated in the upper channel layer. The analytical results are well supported by numerical device simulations, and the physical mechanisms behind these findings are explained along with the analytical investigations.

A new superjunction MOSFET (SJ-MOSFET) architecture with dual built-in Schottky diodes is proposed and studied with numerical TCAD simulations. The study is based on silicon. One Schottky contact is formed to the top of the n-pillar, while the other is formed to the bottom of the p-pillar. During reverse conduction period, the Schottky junctions turn on at a lower voltage than the PN junction. The current flows through n-pillar and p-pillar in parallel, so the potential difference across the PN junction is kept below its turn-on voltage. Thus, minority carrier injection through the PN junction is completely suppressed, leading to a superior reverse recovery performance. Integration of a single Schottky contact to either the n-pillar or the p-pillar cannot completely suppress the turn-on of the PN junction in the SJ-MOSFET, due to the potential drop created by the current through only one type of the pillars. Furthermore, the proposed dual-Schottky SJ-MOSFET reduces the gate charge (QG) and the gate to drain charge (QGD), compared to the conventional SJ-MOSFET, leading to better figures of merit.