In analog fault simulation, the number one challenge is that simulation time could grow rapidly and become prohibitive as the circuit size becomes large. This paper proposes a systematic method to significantly improve the time efficiency in estimating the fault coverage for analog fault simulation. In the proposed method, a circuit under test (CUT) is first partitioned into independent sub-circuits. This is accomplished through mapping the circuit into a graph, decomposing the graph into strongly connected components (SCCs), and generating a sub-circuit for each SCC. The impacts of potential faults directly entering a sub-circuit are then simulated and recorded using the sub-circuits, which is expected to be much more time efficient than fault simulation using the whole circuit, which is much larger in size. Finally, the fault detectability at the given test points is evaluated based on the fault impacts and sensitivity among different sub-circuits. As a first step toward quick estimation of fault coverage, this paper focuses on dc tests. Simulation results show that the fault coverage of dc tests can be estimated sufficiently accurately with simulation time being reduced by 10X for the benchmark circuit, or by approximately the number of SCCs. For a much larger circuit, the number of SCCs is expected to be much larger and the time-saving factor will be much larger.

Multi-site testing saves test time and tests cost by screening multiple chips at once. However, it comes with its issues. As test engineers increase the number of sites on each tester to further save test time and cost, variations are now being observed in measurements from site to site which do not correspond to actual problems in the devices under test. Thus, a cost-effective way to investigate site to site variations and identify sites with issues needs to be developed to ensure high test quality and to rule out possible problems arising from the test hardware. In this paper, regression fitting on a quantile-quantile curve is used to compare the distribution of each site to a theoretical and expected distribution. This is shown to pronounce site to site variations inherent in test data, hence identifying issue-ridden sites with ease. The quantile-quantile plot compares the integrals of two probability density functions in a single plot, thus capturing the location, scale, and skewness of the test data set. This method provides more information to the test engineer than classical statistical methods that rely on single test statistics for distribution comparison and is at no extra cost.

A novel ultrafast and low-cost pipelined analog-to-digital converter (ADC) testing and calibration method is proposed. The ADC nonlinearities are modeled as segmented parameters with interstage gain errors. During the test phase, a pure sine wave is sent as input and the model parameters are estimated from the output data with the system identification method. Significantly, fewer samples are required when compared to traditional histogram testing. The modeled errors are then removed from the digital output codes during the calibration phase. Extensive simulations have been run to verify the correctness and robustness of the proposed method. With just 4000 samples, a 12-bit ADC can be accurately tested and calibrated to achieve less than 1 least significant bit (LSB) integral nonlinearity (INL). Measurement results show that the ADC effective number of bits (ENOB) is improved from 9.7to 10.84 bits and the spurious-free dynamic range (SFDR) is improved by 20 dB after calibration. The chip is fabricated in 40-nm technology and consumes 10.71 mW at a sampling rate of 125 MS/s.

The Digital-to-Analog-Converter (DAC) is one of the fundamental components of Analog and Mixed-signal circuits. Static linearity testing of high resolution high performance DACs traditionally requires a long time and is very expensive. In this paper, a low-cost ultrafast method of testing DACs is presented. The method utilizes a low cost on-board measurement device for capturing the output of the DAC, instead of a precise digital voltmeter. By using a segmented non-parametric model for the DAC's INL curve and thus reducing the number of unknowns, the test time is drastically reduced. Additionally, the linearity requirement on the measurement device is significantly relaxed by removing its non-linearity. The combination of these two methods results in drastic reduction in linearity test cost for DACs.

This article explains the application of BIST for co-testing of embedded data converters wherein precision source and measurement requirements are relaxed. This is illustrated for test of DAC and ADC with equal resolution, namely 14 bits. —Rubin A. Parekhjii, Texas Instruments, India

A method for separating and accurately estimating ADC noise, aperture jitter, and clock jitter is presented for ADC testing and characterization. This significantly relaxes clock jitter requirements and removes the need for high precision test instruments, but still allows ADC specifications like SNR, SNDR and ENOB to be accurately estimated.