An output-capacitorless low-dropout regulator (OCL-LDO) with simple structure and fast transient response is proposed for system-on-chip (SoC) applications. A super source follower is inserted into a cascoded flipped voltage follower to drive the power transistor, which forms a fast-local loop for quick turn-on. A robust overshoot detection circuit consuming only leakage current is proposed for fast turn-off. The combination of these two techniques significantly reduce the overshoot/undershoot voltages and achieve fast settling time during load steps. A simple yet effective additional turn-around stage is added in the error amplifier to improve the positive phase slew rate for potential dynamic voltage scaling (DVS) function in battery-operated systems. The LDO is implemented in a 65 nm CMOS process and it can deliver a 20 mA load current with 0.9 V regulated output and 150 mV dropout voltage. It occupies an active area of 0.01 mm² and can work stably in a load range from 0 to 20 mA with 65μA quiescent current. The measured results show a settling time about 100 ns for load steps from 100μA to 20 mA as well as VREF and VIN steps.

Linearity testing of analog-to-digital converters (ADCs) is very challenging and expensive due to the stringent linearity requirement on the stimulus and the extremely long test time. This paper introduces a novel method for ADC static linearity testing, allowing the stimulus linearity requirement to be significantly relaxed and the test time to be significantly reduced compared to the state-of-art histogram method. Two nonlinear but functionally related input signals are used as the ADC's excitation and a stimulus error removal technique is used to recover test accuracy. With a segmented non-parametric integral nonlinearity model, this method requires much fewer parameters to accurately represent the nonlinearity. The proposed algorithm has been extensively verified and correlated in simulations. This method not only enables low-cost production testing but can also be used for low-cost on-chip built-in self-test. This method is limited to ADCs with segmented architecture such as SAR ADCs, pipeline ADCs, and cyclic ADCs.

A general approach based on a natural basis function expansion to cancel the temperature-curvature of the base-emitter voltage in the bipolar transistors embedded in bandgap references is presented. The proposed method can be applied to the widely used Banba, Kuijk, and Brokaw structures to build references with sub-ppm/°C temperature coefficients. Current version and voltage version embodiments based on a self-bootstrapping concept are provided. Error sources that can potentially affect the reference performance are analyzed and their effects on the temperature coefficient are minimized after trimming. Monte Carlo simulation results confirm that after calibration, temperature drift performance is within the design/trimming target 0.5 ppm/°C. A partially integrated Kuijk-based prototype reference has been designed and fabricated in a 65nm UMC process. Measurement results demonstrated a 1.5 ppm/°C temperature coefficient over a temperature range of 0 °C to 80 °C with a low-cost two-temperature trimming method. With additional trimming, 0.8 ppm/°C performance was achieved.

A new low offset dynamic comparator for high resolution high speed analog-to-digital application has been designed. Inputs are reconfigured from the typical differential pair comparator such that near equal current distribution in the input transistors can be achieved for a meta-stable point of the comparator. Restricted signal swing clock for the tail current is also used to ensure constant currents in the differential pairs. Simulation based sensitivity analysis is performed to demonstrate the robustness of the new comparator with respect to stray capacitances, common mode voltage errors and timing errors in a TSMC 0.18mu process. Less than 10mV offset can be easily achieved with the proposed structure making it favorable for flash and pipeline data conversion applications

Attaining high matching property of the current sources is very important for the design of high-speed high-accuracy current-steering DACs. This paper presents a novel calibration technique-complete-folding, which achieves the high matching accuracy by selectively regrouping current sources into a fully binary-weighted array based on the current comparisons after chip fabrication. The implementation only requires an analog current comparator and some digital circuitry. The minimum requirement of analog circuits makes the complete-folding calibration suitable for the DAC design in the low-voltage process. Statistical results with a behavioral model of a 14-bit segmented DAC in MATLAB show that complete-folding calibration can reduce the total gate area of current sources by a factor of almost 1200 compared to that using intrinsic-accuracy method. Additional results also show that the new calibration technique has the superior performance in compensating random mismatch errors compared with state-of-the-art.

Data converters are among the most widely used components in modern integrated devices and systems. A major challenge is to characterize their performances accurately and cost effectively. The analog-to-digital converter (ADC) standard test requires the input sinusoidal signal to be 3-4 b better than that of the ADC under test. Such high-quality sine waves are extremely difficult to generate and challenging to implement cost effectively. This paper presents a novel method that is capable of generating a high-purity sine wave using a nonlinear digital-to-analog converter (DAC), whose purity is significantly better than the original DAC output. In addition, with the aid of the low-cost DAC-ADC co-testing method, both DAC and ADC linearity information are accurately obtained with only 1 hit per code. Therefore, it is possible to add DAC linearity information to the DAC input codes, which cancels the nonlinearity of the DAC at output to achieve high purity. The proposed method has been validated by extensive simulation and measurement results, which demonstrated its accuracy and robustness against different resolutions, structures, or performance of the ADCs/DACs. With its low cost and easy test setup, such high-purity sine wave can be widely used for various applications where precision testing is required. In addition, the ADC and DAC linearity information is accurately obtained at the same time without any precision instrumentation, which is suitable for accurate DAC-ADC co-testing.