This article explains the application of BIST for co-testing of embedded data converters wherein precision source and measurement requirements are relaxed. This is illustrated for test of DAC and ADC with equal resolution, namely 14 bits. —Rubin A. Parekhjii, Texas Instruments, India

This paper introduces a systematic approach to the design of Direct Current-to-Digital Converter (DIDC) specifically engineered to overcome the limitations of traditional current measurement methodologies in System-on-Chip (SoC) designs. The proposed DIDC addresses critical challenges such as high power consumption, large area requirements, and the need for intermediate analog signals. By incorporating a current mirror in a cascode topology and managing the current across multiple binary-sized branches with the Successive Approximation Register (SAR) logic, the design achieves precise current measurement. A simple comparator, coupled with an isolation circuit, ensures accurate and reliable sensing. Fabricated using the TSMC 180 nm process, the DIDC achieves 8-bit precision without the need for nonlinearity calibration, showcasing remarkable energy efficiency with an energy per conversion of 1.52 pJ, power consumption of 117 µW, and a compact area of 0.016 mm². This innovative approach not only reduces power consumption and area, but also provides a scalable and efficient solution for next-generation semiconductor technologies. The ability to conduct online measurements during both standard operations and in-field conditions significantly enhances the performance and reliability of SoCs, making this DIDC a promising advancement in the field.

Waveform generation as part of on-chip built-in self-test (BIST) circuitry often necessitates sufficient linearity without expensive hardware overhead. Achieving high linearity is critical for accurate signal generation, especially in applications requiring high precision, such as biomedical and instrumentation applications. Currently, achieving the high linearity and precision required in signal generators often relies on costly hardware such as automated test equipment (ATE). This paper presents a DAC-based arbitrary waveform generator (AWG). We use a low-cost DAC and a fully digital on-chip testing and calibration approach to nullify the effect of the DAC’s non-linearity on the generated waveform. The ultra-low cost and high linearity benefit of the proposed waveform generator makes it highly suitable for integration into resource-constrained systems. The proposed approach is validated using simulation results of the small-area DAC designed in TSMC 0.18 μm technology and the testing and calibration algorithms implemented in MATLAB. The DAC, designed with a matching accuracy at only the 5-bit level, is able to generate a signal with an ENOB of 12 bits alongside an SFDR and THD surpassing 100 dB. This high level of signal purity is consistently maintained across 100 Monte Carlo simulations, demonstrating the robustness of the architecture against PVT variations as well as random mismatches.

This brief presents a novel monolithic ultra-low leakage current sensor with large dynamic range. The sensor features an integrated digitizing circuit that generates digital output corresponding to changing leakage current levels, eliminating the need for an explicit ADC. Fabricated in a 180nm BCD process, the sensor occupies just 0.0234mm² of area, consumes 3.1mW of power and operates at 3.125 MHz. It achieves a dynamic range of 25 pA to 5.5μA, outperforming previous publications by several orders of magnitude. Measurement results demonstrate the sensor’s accuracy, with INL and DNL remaining below 0.4 LSB across a temperature range of −40°C to 125°C. The sensor’s ultra-low sensing capability and wide dynamic range make it suitable for time-dependent dielectric breakdown (TDDB) characterization and in-field reliability monitoring of circuits, enhancing reliability assessments in safety-critical systems.

This paper presents a three-segment interpolating Digital-to-Analog Converter (DAC) that employs a redundancy-based interpolation scheme and digital calibration to enhance linearity. The proposed architecture consists of a Most Significant Bit (MSB) resistor string DAC, an Intermediate Significant Bit (ISB) resistor string DAC, and a Least Significant Bit (LSB) interpolating differential buffer. The MSB segment uses a split-unit resistor structure ($r_A,r_B$) to improve post-calibration differential nonlinearity (DNL) by minimizing voltage step errors. A fully digital calibration algorithm is implemented to compensate for process variations, component mismatches, and finite switch resistance, ensuring a highly linear DAC output. The proposed 16-bit DAC is implemented in a 180 nm CMOS process and is segmented into a 5-bit MSB stage, a 5-bit ISB stage, and a 6-bit LSB stage. The structure achieves post-calibration integral nonlinearity (INL) and differential nonlinearity (DNL) values of less than ±1 LSB. Simulation results validate the proposed design, demonstrating enhanced linearity and reduced area overhead compared with conventional segmented architectures.

The first divider in an integer- or fractional-N frequency synthesizer runs at the full oscillator frequency and so constrains both the speed and the power of the loop. Current-mode logic (CML) reaches high speed but draws a constant bias current independent of activity, whereas a fully static-CMOS (all-digital) divider draws only dynamic and leakage current at the cost of much greater timing sensitivity to process, voltage, and temperature (PVT) variation. This paper presents a wide-range all-digital multi-modulus divider in a 22 nm fully depleted silicon-on-insulator (FDSOI) technology, characterized entirely by post-layout and Monte Carlo simulation, together with the methodology that makes the timing-sensitive digital approach robust. The all-digital chain exhibits three PVT failure modes, setup at the slow-hot corner, hold at the fast-cold corner, and internal duty-cycle collapse at the skewed corners; each is predicted analytically and closed by a three-method scheme built on the FDSOI back gate, a per-stage delay trim, and a systematic integral-nonlinearity trim. The divider covers N=8 to 127 at up to 39.5 GHz at the typical corner, with every process corner held at or above 35 GHz by back-gate compensation, the highest speed among the compared dividers and the only one with explicit PVT compensation. At the 33 GHz target it consumes 5.3 mW at N=127 (6.2 GHz/mW) with an activity-scaling supply current, benchmarked against the measured power of published CML dividers. Per-die body-bias and trim raise the Monte Carlo yield from 78% to 99.3%, at 150 fs additive jitter, in a compact 0.005 mm² core.