CMOS technology dominates the semiconductor industry, and the reliability of MOSFETs is a key issue. To optimize chip design, trade-offs between reliability, speed, power consumption, and cost must be carried out. This requires modeling and prediction of device instability, and a major source of instability is device aging, where defects gradually build up and eventually cause malfunction of circuits. This paper first gives an overview of the major aging processes and discusses their relative importance as CMOS technology developed. Attentions are then focused on the negative and positive bias temperature instabilities (NBTI and PBTI), mainly based on the early works of the authors. The aim is to present the As-grown-Generation (AG) model, which can be used not only to fit the test data but also to predict long-term BTI at low biases. The model is based on an in-depth understanding of the different types of defects and the experimental separation of their contributions to BTI. The new measurement techniques developed to enable this separation are reviewed. The physical processes responsible for BTI are explored, and the reasons for the failure of the early models in predicting BTI are discussed.

A recently reported zero impact ionization and zero subthreshold swing device Z2FET is a promising candidate for capacitor-less dynamic random access memory (DRAM) memory cell. In the memory operation, data retention time determines refresh frequency and is one of the most important memory merits. In this paper, we have systematically investigated the Z2FET retention time based on a newly proposed characterization methodology. It is found that the degradation of HOLD “0” retention time originates from the gated-silicon on insulator (SOI) portion rather than the intrinsic-SOI region of the Z2FET. Electrons accumulate under front gate and finally collapse the potential barrier turning logic “0”-“1.” It appears that Shockley-Read-Hall (SRH) generation is the main source for electrons accumulation. Z2FET scalability has been investigated in terms of retention time. As the Z2FET is downscaled, the mechanism dominating electrons accumulation switches from SRH to parasitic injection of electrons from the cathode. The results show that the downscaling of Lg has little effect on data “0” retention, but Lin is limited to ~125 nm. An optimization method of the fabrication process is proposed based on this new understanding, and Lin can be further scaled down to 75 nm. We have demonstrated by 2-D TCAD simulation that Z2FET is a promising DRAM cells' candidate particularly for Internet-of-Things applications.

Modelling of the interaction between Hot Carrier Aging (HCA) and Positive Bias Temperature Instability (PBTI) has been considered as one of the main challenges in nanoscale CMOS circuit design. Previous works were mainly based on separate HCA and PBTI instead of Interacted HCA-PBTI Degradation (IHPD). The key advance of this work is to develop a methodology that enables accurate modelling of IHPD through understanding the charging/discharging and generation kinetics of different types of defects during the interaction between HCA and PBTI. It is found that degradation during alternating HCA and PBTI stress cannot be modelled by independent HCI/PBTI. Different stress sequence, i.e. HCA-PBTI-HCA and PBTI-HCA-PBTI, lead to completely different degradation kinetics. Based on the Cyclic Anti-neutralization Model (CAM), for the first time, IHPD has been accurately modelled for both short and long channel devices. Complex degradation mechanisms and kinetics can be well explained by our model. Our results show that device lifetime can be underestimated by one decade without considering interaction.

Memory technology requires high density, large volume memory arrays in the limited chip real estate. Z2FET memory architecture has demonstrated advantages for CMOS technology implementation including compatibility and scalability, novel capacitor-less memory action, area reduction, and sharp switching characteristics. As a candidate of e-DRAM applications [1-4], minimizing cell dimensions is one of the key targets in order to deliver Z2FET competitive advantage in memory technology design and applications. The cell area is mainly determined by the Z2FET length and width. Therefore, the scaling study the Z2FET length is crucial in achieving high-density storage solutions.