This paper presents a reconfigurable SRAM-based physically unclonable function (PUF) topology with multiple challenge-response pairs (CRPs) per cell. The proposed PUF structure enables a very large CRP space by connecting additional pull-up and pull-down paths to each SRAM cell. These alternate pathways to the supply rail and ground are activated by the challenge inputs, which effectively reconfigure the transfer characteristics of each cross-coupled inverter. A newly proposed response instability detector improves bit error rate (BER) performance by discarding unstable response. In addition, the proposed PUF adds indirect challenges by scrambling the responses using a Galois linear feedback shift register (LFSR). The proposed PUF can be applied to a wider range of applications as a CRP PUF because it has multiple CRPs in addition to the small area and fast operating speed, which are the advantages of the conventional SRAM structure. In order to verify the performance of the proposed architecture, a 32×32-bit reconfigurable SRAM PUF array with 32-bit challenge is implemented in a 65 nm CMOS process. Experimental results show a core area of 88.867 μ m ² /bit, energy efficiency of 0.082 pJ/bit, and inter-chip Hamming distance (HD) of 48.93% across 40 chips. By applying an unstable bit discard (UBD) scheme, BER is improved from 13.7% to 0.9%. Compared to the state-of-the-art, the proposed PUF is shown to be highly competitive in area, throughput and energy efficiency.

This paper presents a post-processing algorithm for a true random number generator (TRNG). Once the randomness of security key generation deteriorates for any reason, the entire chain of the security system can be compromised, increasing the odds of it being exploited by an attacker to retrieve information. Considering the change in the distribution of the RNG output sequence due to variations in the operating environment or the occurrence of aging phenomena in silicon-integrated circuits, a robust post-processing algorithm must be applied to an intrinsic TRNG to ensure the sustainability of a security system. Targeting high-level cryptography systems complying with the NIST 800-22a requirements, the proposed algorithm significantly improves the Hamming weight (HW) and successfully passes the NIST criteria while sacrificing approximately 20% of the entire number of available bits. The proposed algorithm improves the randomness of the TRNG through a sequential cell- and bit-level discarding technique, a cell-discard method, and focuses on improving the overall HW of the TRNG while the subsequent bit- discard method performs a Chi-square (${\chi }^2$) test. To prove the concept, we programmed the proposed algorithm in a FPGA and configured the output of the manufactured TRNG chip to be post-processed and stored into on-board memory in real time. For five different ring-oscillator-based TRNG prototypes (fully custom designed in the 65 nm CMOS process), the failed intrinsic TRNG output sequences were respectively post-processed, resulting in all surpassing the NIST 800-22a requirements.