This paper presents a reconfigurable SRAM-based physically unclonable function (PUF) topology with multiple challenge-response pairs (CRPs) per cell. The proposed PUF structure enables a very large CRP space by connecting additional pull-up and pull-down paths to each SRAM cell. These alternate pathways to the supply rail and ground are activated by the challenge inputs, which effectively reconfigure the transfer characteristics of each cross-coupled inverter. A newly proposed response instability detector improves bit error rate (BER) performance by discarding unstable response. In addition, the proposed PUF adds indirect challenges by scrambling the responses using a Galois linear feedback shift register (LFSR). The proposed PUF can be applied to a wider range of applications as a CRP PUF because it has multiple CRPs in addition to the small area and fast operating speed, which are the advantages of the conventional SRAM structure. In order to verify the performance of the proposed architecture, a 32×32-bit reconfigurable SRAM PUF array with 32-bit challenge is implemented in a 65 nm CMOS process. Experimental results show a core area of 88.867 μ m ² /bit, energy efficiency of 0.082 pJ/bit, and inter-chip Hamming distance (HD) of 48.93% across 40 chips. By applying an unstable bit discard (UBD) scheme, BER is improved from 13.7% to 0.9%. Compared to the state-of-the-art, the proposed PUF is shown to be highly competitive in area, throughput and energy efficiency.

This paper presents a lightweight and secure data communication protocol tailored for resource-constrained IoT environments. The proposed method integrates Challenge-Response Pair (CRP) Physically Unclonable Functions (PUFs) and a True Random Number Generator (TRNG) to eliminate the need for non-volatile key storage, thereby significantly enhancing resistance against physical attacks and key extraction threats. In contrast to conventional public key authentication methods such as those employed in Pretty Good Privacy (PGP), the protocol replaces asymmetric key operations with CRP-PUFs and hash-based message authentication codes (HMACs), effectively removing the need for key pair generation, key distribution, and private key encryption. To ensure stability in PUF responses under environmental variations, the protocol applies majority voting and BCH error correction codes. It further leverages a large CRP space and incorporates dynamic CRP updates to ensure backward secrecy. In addition, elliptic curve cryptography (ECC) point validation is used to defend against fault injection attacks, collectively offering strong resistance against cloning, brute-force, and implementation-level attacks. While preserving the core cryptographic functions of PGP—such as session key wrapping, ECDSA-based digital signatures, and AES encryption—the proposed protocol dynamically derives all secret keys from hardware-based entropy sources. As a result, it achieves comprehensive security guarantees including authentication, integrity, confidentiality, and non-repudiation, while significantly reducing computational complexity and authentication latency compared to conventional ECC-based schemes. The protocol’s correctness and security are formally verified using ProVerif and Mao-Boyd logic, and its practical feasibility is demonstrated through a compact single-chip implementation, making it highly suitable for real-world industrial IoT deployments.

This paper introduces a novel TRNG architecture that employs a wave converter to generate random outputs from the jitter noise in a customized ring oscillator (RO). Using a current-starved inverter, the proposed RO offers the option of operating three different oscillation frequencies from a single oscillator. To assess its performance, the core TRNG proposed in this work was designed with multiple samples, employing various transistor sizes for 28 nm CMOS processes. The measurements show that only a small number of measured TRNG samples passed the randomness NIST SP 800-22 tests, which is a common problem, not only with the proposed TRNG but also with other TRNG structures. To solve this issue, a lightweight post-processing algorithm using the Photon hash function was newly applied to the proposed TRNGs topology. The lightweight Photon hash function-based post-processing was implemented with the proposed TRNG topology in a 28 nm CMOS process. The design occupies 16,498 µm², with a throughput of 0.0142 Mbps and power consumption of 31.12 mW. Measurements showed significant improvement, with a 50% increase in chips passing the NIST SP 800-22 tests. Compared with the conventional DRBG post-processing method, the proposed lightweight Photon post-processing reduces area occupation by five times and power consumption by 65%.

This paper introduces an area-optimized and power-efficient implementation of the Cipher Block Chaining (CBC) mode for an ultra-lightweight block cipher, PRESENT, and the Keyed-Hash Message Authentication Code (HMAC)-expanded PHOTON by using a feedback path for a single block in the scheme. The proposed scheme is designed, taped out, and integrated as a System-on-a-Chip (SoC) in a 65-nm CMOS process. An experimental analysis and comparison between a conventional implementation of CBC-PRESENT/HMAC-PHOTON with the proposed feedback basis is performed. The proposed CBC-PRESENT/HMAC-PHOTON has 128-bit plaintext/text and a 128-bit secret key, which have a gate count of 5683/20,698 and low power consumption of 1.03/2.62 mW with a throughput of 182.9/14.9 Mbps at the maximum clock frequency of 100 MHz, respectively. The overall improvement in area and power dissipation is 13/50.34% and 14.87/75.28% when compared to a conventional design.

This article presents a novel lightweight authentication and secure communication protocol and its energy-efficient system-on-chip (SoC) implementation for resource-constrained industrial Internet of Things devices operating in unattended and physically exposed environments. The proposed protocol supports device-to-server verification, device-to-device mutual authentication, and session key establishment without storing long-term shared secret keys in nonvolatile memory (NVM), thereby mitigating physical key-extraction and cloning attacks common in exposed industrial deployments. Device-specific keying material is regenerated on demand from an on-chip challenge-response pairs (CRPs)-based physical unclonable function (PUF). Formal security analysis using Mao–Boyd logic and Scyther-based verification demonstrates resistance to replay, man in the middle, impersonation, side-channel, and physical cloning attacks, while protocol-level evaluation confirms low computational cost achieved through exclusive use of symmetric cryptography and a single PUF evaluation per session. Building on the proposed protocol, an energy-efficient SoC architecture is implemented and evaluated. The fabricated design in a 28-nm CMOS process occupies 191 kGE and operates at 25 MHz from a 0.9-V supply. Measurement results show that the complete authentication and key-establishment procedure consumes 11.48 $\mathrm{\mu }$J. The implemented protocol achieves a 1.4× increase in total energy efficiency compared to state-of-the-art cryptographic architecture implementing DTLS and the double ratchet protocol. The security and robustness of the hardware implementation are further assessed through circuit-level analysis of the CRPs-PUF. These analysis results demonstrate the suitability of the proposed protocol and hardware architecture for scalable and long-lifetime industrial IoT deployments.