This paper demonstrates a multi-bit/cycle successive-approximation register (SAR) analog-to-digital converter (ADC) architecture for low-power and high-speed operation. The proposed dual reference shifting and interpolation technique reduces the power and area overhead of the multi-bit/cycle SAR architecture, allowing for a higher number of bit quantization for each conversion cycle and thus, a higher conversion rate. To prove the concept, a 12-bit 32-way time-interleaved 4-b/cycle SAR ADC prototype is fabricated in 65-nm CMOS technology. The ADC prototype can be configured with multiple sampling rates (1.6, 3.2, and 6.4 GS/s). It measures a peak effective number of bits (ENOB) of 10.9 bits at 6.4 GS/s and 9.4 ENOB at the maximum input frequency of 1 GHz. The prototype achieves a Schreier figure-of-merit (FOMSchreier) of 154.9 dB at 6.4-GS/s sampling rate.

This paper presents an ultra-small physical unclonable function (PUF) chip structure to protect data in compact IoT sensor devices. The proposed PUF has far fewer transistors and a reduced active area compared to the conventional strong PUF with multiple challenge response pairs (CRPs). According to the manufacturing process variations, the conventional SRAM-based PUF uses a switching transistor and a main transistor to implement multiple CRPs, whereas the proposed structure adds the function of a switching transistor to a single main transistor, controlling the body voltage to switch the transistor. This unified and simple PUF structure results in significant silicon area reduction. For a PUF with a 32-bit challenge, the number of transistors is significantly reduced by 40%; the active area of the conventional structure is $57.78~\mu m^{2}$ while the area of the proposed structure is $36.4~\mu m^{2}$ . Overall, an active area reduction of 38% is realized with the same number of CRPs. Here, we implemented an SRAM-based PUF system with a 32-bit challenge, a 1024-bit response, and 160 million CRPs. PUF core cell shows energy efficiency of 0.09 pJ/bit. The inter-Hamming distance is 48.89%, while the intra-Hamming distance is 1.2% after data post-processing, i.e., discarding unstable bits. A prototype chip is implemented in the 65nm CMOS process with a supply voltage of 1.2V. Compared to the prior arts, the proposed prototype is shown effective silicon area reduction while maintaining remarkable energy efficiency.

This paper demonstrates an asynchronous successive-approximation-register (SAR) analog-to-digital converter (ADC) architecture with an embedded passive gain technique for lowpower and high-speed operation. The proposed passive gain technique relaxes the noise requirement of the comparator and reuses the existing capacitor DAC in SAR for minimal overhead. An additional time-out scheme is adopted to advance the SAR conversion whenever the comparator takes longer time to resolve, which improves the overall conversion rate. To prove the concept, an 11-bit ADC prototype was fabricated in 65 nm CMOS technology. The prototype measured a peak effective number of bits (ENOB) of 10.2 and a spurious-free dynamic range (SFDR) of 75.2 dB at a 95-MS/s sampling rate with 1.36-mW power consumption from a 1.1 V supply. The measured static differential nonlinearity (DNL) and integral nonlinearity (INL) were less than ± 0.84 LSB with a differential input swing of 1.6 V _pp .

This paper presents a novel reconfigurable SRAM CRP PUF that can achieve high reliability and randomness. In conventional reconfigurable SRAM CRP PUFs, imprecise timing control can produce a biased response output, which is typically attributed to mismatches in the connection of input control signals to the two inverter arrays in the layout floorplan. We propose a timing control scheme along with the addition of an adjunct NMOS transistor to address this issue. This eliminates the connection mismatches for the challenge and word-line inputs to the two inverter arrays. Furthermore, we employ symmetric layout techniques to achieve the randomness of response output. The symmetric arrangement of the two inverter arrays maximizes the inherent random output characteristics derived from process variation. The pre-charge input signal is symmetrically connected to each array to prevent delay mismatches. A 16 × 9-bit reconfigurable PUF array is fabricated by using a 180 nm CMOS process, with a PUF cell area of $1.2$ × ${10}^4$ F${}^2$/bit. The experimental results demonstrate an inter Hamming distance of 0.4949 across 40 chips and an intra Hamming distance of 0.0167 for a single chip in 5000 trials. The measured worst bit error rate (BER) is 4.86% at the nominal point (1.8 V, 25 °C). The proposed prototype exhibits good reliability and randomness, as well as a small silicon area when compared to the conventional SRAM CRP PUFs.

This paper introduces a novel TRNG architecture that employs a wave converter to generate random outputs from the jitter noise in a customized ring oscillator (RO). Using a current-starved inverter, the proposed RO offers the option of operating three different oscillation frequencies from a single oscillator. To assess its performance, the core TRNG proposed in this work was designed with multiple samples, employing various transistor sizes for 28 nm CMOS processes. The measurements show that only a small number of measured TRNG samples passed the randomness NIST SP 800-22 tests, which is a common problem, not only with the proposed TRNG but also with other TRNG structures. To solve this issue, a lightweight post-processing algorithm using the Photon hash function was newly applied to the proposed TRNGs topology. The lightweight Photon hash function-based post-processing was implemented with the proposed TRNG topology in a 28 nm CMOS process. The design occupies 16,498 µm², with a throughput of 0.0142 Mbps and power consumption of 31.12 mW. Measurements showed significant improvement, with a 50% increase in chips passing the NIST SP 800-22 tests. Compared with the conventional DRBG post-processing method, the proposed lightweight Photon post-processing reduces area occupation by five times and power consumption by 65%.

Electric vehicles (EVs) have already been acknowledged to be the most viable solution to the climate change that the entire globe has long been combating. Along the same line, it is a salient subject to expand the availability of EV charging infrastructure, which quintessentially necessitates the optimization of the charger’s locations. This paper proposes to formulate the optimal EV charger location problem into a facility location problem (FLP). As an effort to find an efficient method to solve the well-known nonpolynomial deterministic (NP) hard problem, we present a comparative quantification among several representative solving techniques. This paper features two comprehensive case studies representing regions with an average and a high density of EVs. As such, this paper shows that the proposed framework can lead to successful location optimization with adequate refinement of solving techniques.