As one of the key components in mechanical systems, rotatory machine plays a significant role in safe and stable operation. Accurate prediction of the Remaining Useful Life (RUL) of rotatory machine contributes to realization of intelligent operation and maintenance for mechanical manufacturing. In order to overcome the limitations of traditional machine learning algorithms in dealing with complex nonlinear signals, a novel prediction framework for RUL of rotatory machine based on deep learning is proposed in this paper. One-dimensional convolutional neural network is utilized to extract local features from the original signal sequence. In addition, the proposed framework analyzes sensor signals and predicts RUL by combining Long Short-Term Memory (LSTM) network with attention mechanism. Multi-layer LSTM is set up to extract useful temporal features layer by layer and improve the robustness of the model, while attention mechanism is able to effectively solve the problem of information loss in the long-distance signal transmission of LSTM. Through the feature extraction of multi-layer LSTM and the strong supervision ability of attention mechanism, the RUL of rotatory machine can be accurately predicted. The experimental results show that the proposed method for RUL estimation is efficient and has higher prediction accuracy than the traditional machine learning algorithms.

This article presents a high-efficiency fast transient constant on -time (COT) control dc–dc buck converter for the Internet of Things applications. The current reused current sensor is proposed to enhance the loop stability and improve the power conversion efficiency at light load. Input current is sensed and added to the feedback voltage of the dc–dc converter to increase the sensed output ripple voltage. Fast transient dc-offset cancelation technique is introduced to achieve a fast transient recovery time and to cancel the output dc offset. This chip is fabricated with a 0.13- μ m CMOS process. A standard supply voltage of 7–15 V is applied to produce the output voltage of 5–5.33 V. The total die area is 2 mm × 1.5 mm. The settling time is 17 μ s. The transient recovery time from light to heavy load and from heavy load to light load are 3 μ s and 2.7 μ s, respectively, with a maximum dc offset of 3.5 mV. The overshoot voltage is 85 mV and the undershoot voltage is 72 mV. The peak efficiency of the proposed design is 95.56% at 0.5 A and efficiency at the light load of 10 mA is 84.60%.

An energy efficient, low-power 10-bit asynchronous successive approximation register (SAR) analog-to-digital (ADC) converter with the sampling frequency of 8 MS/s is presented in the proposed paper for IEEE 802.15.1 IoT sensor based applications. An improved common mode charge redistribution algorithm is proposed for binary weighted SAR ADC. The proposed method uses available VCM level for SAR ADC conversion, and this method reduces the switching power more than 12% without any additional DAC driver as compared to merged capacitor switching (MCS). Mathematical analysis of the proposed switching scheme results in the lower or equal power consumption for every digital code as compared to MCS. A two stage dynamic latched comparator with adaptive power control (APC) technique is used to optimize the overall efficiency. Furthermore, to minimize the digital part power consumption, a modified asynchronous SAR logic with digitally controlled delay cells is proposed. High efficiency with low power consumption makes it suitable for low power devices especially for IEEE 802.15.1 IoT sensor based applications. The proposed prototype is implemented using 1P6M 55 nm complementary metaloxide-semiconductor (CMOS) technology. The measurement results that the proposed circuit achieves are 9.3 effective number of bits (ENOB) with signal-to-noise and distortion ratio (SNDR) of 58.05 dB at a sampling rate of 8 MS/s. The power consumption of SAR ADC is 45 μW when operated at 1 V power supply. INDEX.

In this paper, a self-threshold voltage (V_th) compensated Radio Frequency to Direct Current (RF-DC) converter operating at 900 MHz and 2.4 GHz is proposed for RF energy harvesting applications. The threshold voltage of the rectifying devices is compensated by the bias voltage generated by the auxiliary transistors and output DC voltage. The auxiliary transistors compensate the threshold voltage (V_th) of the PMOS rectifying device while the threshold voltage (V_th) of the NMOS rectifying device is compensated by the output DC voltage. The proposed RF-DC converter was implemented in 180 nm Complementary Metal-Oxide Semiconductor (CMOS) technology. The experimental results show that the proposed design achieves better performance at both 900 MHz and 2.4 GHz frequencies in terms of PCE, output voltage, sensitivity, and effective area. The peak power conversion efficiency (PCE) of 38.5% at −12 dBm across a 1 MΩ load for 900 MHz frequency was achieved. Similarly, for 2.4 GHz frequency, the proposed circuit achieves a peak PCE of 26.5% at −6 dBm across a 1 MΩ load. The proposed RF-DC converter circuit shows a sensitivity of −20 dBm across a 1 MΩ load and produces a 1 V output DC voltage.

In this research work, a reconfigurable 2.45-GHz RF-DC converter realized in a 180-nm complementary metal-oxide semiconductor (CMOS) technology is proposed to efficiently harvest electromagnetic energy. The proposed circuit is composed of a low-power path rectifier, a high-power path rectifier, and an adaptive path control (APC) circuit. The APC circuit is made-up of a comparator, two switches, and an inverter. The APC circuit senses the output voltages of the low-power path and the high-power path rectifiers and generates a control signal to automatically switch the proposed circuit between the lower-power path and the high-power path operation depending upon RF input power level. The proposed circuit obtains more than 20% measured power conversion efficiency (PCE) from −6 dBm to 11 dBm input power range with maximum efficiencies of 41% and 45% at 1 and 6 dBm input powers, respectively, for 5 kΩ load resistance. In addition, the proposed circuit shows excellent performance at 900 MHz and 5.8 GHz frequencies.

A low power 12-bit, 20 MS/s asynchronously controlled successive approximation register (SAR) analog-to-digital converter (ADC) to be used in wireless access for vehicular environment (WAVE) intelligent transportation system (ITS) sensor based application is presented in this paper. To optimize the architecture with respect to power consumption and performance, several techniques are proposed. A switching method which employs the common mode charge recovery (CMCR) switching process is presented for capacitive digital-to-analog converter (CDAC) part to lower the switching energy. The switching technique proposed in our work consumes 56.3% less energy in comparison with conventional CMCR switching method. For high speed operation with low power consumption and to overcome the kick back issue in the comparator part, a mutated dynamic-latch comparator with cascode is implemented. In addition, to optimize the flexibility relating to the performance of logic part, an asynchronous topology is employed. The structure is fabricated in 65 nm CMOS process technology with an active area of 0.14 mm². With a sampling frequency of 20 MS/s, the proposed architecture attains signal-to-noise distortion ratio (SNDR) of 65.44 dB at Nyquist frequency while consuming only 472.2 µW with 1 V power supply.