This article presents a high-efficiency fast transient constant on -time (COT) control dc–dc buck converter for the Internet of Things applications. The current reused current sensor is proposed to enhance the loop stability and improve the power conversion efficiency at light load. Input current is sensed and added to the feedback voltage of the dc–dc converter to increase the sensed output ripple voltage. Fast transient dc-offset cancelation technique is introduced to achieve a fast transient recovery time and to cancel the output dc offset. This chip is fabricated with a 0.13- μ m CMOS process. A standard supply voltage of 7–15 V is applied to produce the output voltage of 5–5.33 V. The total die area is 2 mm × 1.5 mm. The settling time is 17 μ s. The transient recovery time from light to heavy load and from heavy load to light load are 3 μ s and 2.7 μ s, respectively, with a maximum dc offset of 3.5 mV. The overshoot voltage is 85 mV and the undershoot voltage is 72 mV. The peak efficiency of the proposed design is 95.56% at 0.5 A and efficiency at the light load of 10 mA is 84.60%.

In this paper, a self-threshold voltage (V_th) compensated Radio Frequency to Direct Current (RF-DC) converter operating at 900 MHz and 2.4 GHz is proposed for RF energy harvesting applications. The threshold voltage of the rectifying devices is compensated by the bias voltage generated by the auxiliary transistors and output DC voltage. The auxiliary transistors compensate the threshold voltage (V_th) of the PMOS rectifying device while the threshold voltage (V_th) of the NMOS rectifying device is compensated by the output DC voltage. The proposed RF-DC converter was implemented in 180 nm Complementary Metal-Oxide Semiconductor (CMOS) technology. The experimental results show that the proposed design achieves better performance at both 900 MHz and 2.4 GHz frequencies in terms of PCE, output voltage, sensitivity, and effective area. The peak power conversion efficiency (PCE) of 38.5% at −12 dBm across a 1 MΩ load for 900 MHz frequency was achieved. Similarly, for 2.4 GHz frequency, the proposed circuit achieves a peak PCE of 26.5% at −6 dBm across a 1 MΩ load. The proposed RF-DC converter circuit shows a sensitivity of −20 dBm across a 1 MΩ load and produces a 1 V output DC voltage.

In this article, a 15-W quadruple-mode reconfigurable wireless power-receiving unit with high efficiency for Inductive coupling and magnetic resonance-based standards, such as wireless power consortium (WPC), power matters alliance (PMA), alliance for wireless power (A4WP), and magnetic secure transmission (MST) applications is proposed. Quadruple-mode gate controller(QMGC) is proposed in quadruple-mode synchronous rectifier to manage sizes of core and drivers which results in maximum power conversion efficiency (PCE) for each mode based on conduction and switching losses. In QMGC, switchable zero voltage and current sensing block is proposed for WPC/PMA to maximize PCE regardless of load current variations. For A4WP mode, a digitally controlled delay adjustment block is adapted to minimize power consumption while compensating for delay which results in reverse leakage current and power loss. Finally, for MST mode, low power TX (LPTX) block is implemented to minimize current consumption so that burden on battery can be minimized. A high-resolution current sensor is proposed in low-drop out regulator to sense current for overcurrent limit and overcurrent protection. The measured PCE of proposed system at 15 W are 95.3% and 92.3% for WPC/PMA and A4WP mode, respectively. For MST, power consumption is reduced to 35% courtesy LPTX block.

In this research work, a reconfigurable 2.45-GHz RF-DC converter realized in a 180-nm complementary metal-oxide semiconductor (CMOS) technology is proposed to efficiently harvest electromagnetic energy. The proposed circuit is composed of a low-power path rectifier, a high-power path rectifier, and an adaptive path control (APC) circuit. The APC circuit is made-up of a comparator, two switches, and an inverter. The APC circuit senses the output voltages of the low-power path and the high-power path rectifiers and generates a control signal to automatically switch the proposed circuit between the lower-power path and the high-power path operation depending upon RF input power level. The proposed circuit obtains more than 20% measured power conversion efficiency (PCE) from −6 dBm to 11 dBm input power range with maximum efficiencies of 41% and 45% at 1 and 6 dBm input powers, respectively, for 5 kΩ load resistance. In addition, the proposed circuit shows excellent performance at 900 MHz and 5.8 GHz frequencies.

A low power 12-bit, 20 MS/s asynchronously controlled successive approximation register (SAR) analog-to-digital converter (ADC) to be used in wireless access for vehicular environment (WAVE) intelligent transportation system (ITS) sensor based application is presented in this paper. To optimize the architecture with respect to power consumption and performance, several techniques are proposed. A switching method which employs the common mode charge recovery (CMCR) switching process is presented for capacitive digital-to-analog converter (CDAC) part to lower the switching energy. The switching technique proposed in our work consumes 56.3% less energy in comparison with conventional CMCR switching method. For high speed operation with low power consumption and to overcome the kick back issue in the comparator part, a mutated dynamic-latch comparator with cascode is implemented. In addition, to optimize the flexibility relating to the performance of logic part, an asynchronous topology is employed. The structure is fabricated in 65 nm CMOS process technology with an active area of 0.14 mm². With a sampling frequency of 20 MS/s, the proposed architecture attains signal-to-noise distortion ratio (SNDR) of 65.44 dB at Nyquist frequency while consuming only 472.2 µW with 1 V power supply.

This paper presents an energy-efficient low power 10-b 8-MS/s asynchronous successive approximation register (SAR) analog-to-digital (ADC) converter. An inverted common-mode charge recovery technique is proposed to reduce the switching energy and to improve the linearity of the digital-to-analog converter (DAC). The proposed switching technique consumes only 149 CV_REF² switching energy for the 10-bit case. A rail-to-rail dynamic latch comparator is implemented with adaptive power control for better power efficiency. Additionally, to optimize the power consumption and performance of the logic part, a modified asynchronous type SAR control logic with digitally controllable delay cells is adopted. An on-chip reference voltage generator is also designed with an ADC core for practical use. The structure is realized using 55-nm complementary metal–oxide–semiconductor (CMOS) process technology. The proposed architecture achieves an effective number of bits (ENOB) of 9.56 bits and a signal-to-noise and distortion ratio (SNDR) level of 59.3 dB with a sampling rate of 8 MS/s at measurement level. The whole architecture consumes only 572 µW power when a power supply of 1 V is applied.