This paper presents a reconfigurable radio frequency to direct current (RF-DC) converter operating at 902 MHz frequency designed to efficiently harvest RF signals and convert into useable DC voltages for RF energy harvesting applications. The proposed scheme employs a dual-path, a series (lowpower) path and a parallel (high-power) path, to maintain high power conversion efficiency (PCE) over wide input power range. The dual-path is composed of two identical rectifier blocks utilizing internal threshold voltage cancellation (IVC) technique to efficiently compensate the threshold voltage of the transistors used as rectifying devices. An adaptive control circuit (ACC) consisting of a comparator, an inverter and three switches is used in the proposed scheme. The ACC activates the series path or the parallel path to maximize the harvested power based on the input power range. The proposed scheme is designed and fabricated in a 180 nm complementary metal-oxide semiconductor (CMOS) technology. The measurement results show that PCE of the proposed circuit is above 20% from -18 dBm to -5 dBm, maintaining 13-dB input power range with peak PCE of 33% at -8 dBm for 200 kΩ load resistance. The proposed circuit demonstrates -20.2 dBm sensitivity across 1 MΩ load resistance while producing 1 V output DC voltage.

This article presents a high-efficiency fast transient constant on -time (COT) control dc–dc buck converter for the Internet of Things applications. The current reused current sensor is proposed to enhance the loop stability and improve the power conversion efficiency at light load. Input current is sensed and added to the feedback voltage of the dc–dc converter to increase the sensed output ripple voltage. Fast transient dc-offset cancelation technique is introduced to achieve a fast transient recovery time and to cancel the output dc offset. This chip is fabricated with a 0.13- μ m CMOS process. A standard supply voltage of 7–15 V is applied to produce the output voltage of 5–5.33 V. The total die area is 2 mm × 1.5 mm. The settling time is 17 μ s. The transient recovery time from light to heavy load and from heavy load to light load are 3 μ s and 2.7 μ s, respectively, with a maximum dc offset of 3.5 mV. The overshoot voltage is 85 mV and the undershoot voltage is 72 mV. The peak efficiency of the proposed design is 95.56% at 0.5 A and efficiency at the light load of 10 mA is 84.60%.

This letter presents a dual-band (0.902 and 2.45 GHz) radio frequency (RF)-dc CMOS converter employing the internal threshold voltage cancelation (IVC) technique to harvest electromagnetic energy. The realized RF-dc CMOS converter maintains high power conversion efficiency (PCE) by passively reducing the threshold voltage of the forward-biased transistors so as to increase the harvested power, and increases the threshold voltage of the reverse-biased transistors to reduce the leakage current. More than 20% measured PCE is achieved at 0.902 GHz from -9 to 10-dBm input power range and a peak PCE of 47% is obtained at 1 dBm. At 2.45-GHz band, more than 11% measured PCE is achieved from -2 to 15 dBm input power range and a peak PCE of 27.1% is obtained at 6 dBm. A single-stage RF-dc CMOS converter is realized in 180-nm CMOS technology and it can serve as a good reference to multiband CMOS energy harvesting design in the future.

This article presents a power-efficient hybrid energy-harvesting system that scavenges energy from solar, vibration, and radio frequency (RF) energy sources and converts into regulated output dc voltage courtesy buck–boost dc–dc converter. The proposed architecture incorporates tetra-paths for maintaining high power conversion efficiency (PCE) over extended input power range (−10 to 30 dBm). A time-domain maximum power point tracking technique is proposed for solar energy harvester. A high-efficiency full wave rectifier is designed for triboelectric rectifier. A 5.8-GHz RF-dc converter with adaptive matching is proposed to increase dynamic range of the input power. The chip is implemented in 0.18-µm bipolar-CMOS-DMOS process. The die area of the chip is 2.8 mm × 5.0 mm, including the pads. The solar and triboelectric energy harvesters achieve a measured peak efficiencies of 75.4% and 92.3%, respectively. The high-power 5.8-GHz RF-dc converter achieves measured PCE of 76% at 30 dBm input power. The low-power dual-band RF-dc converter operating at 900 MHz and 2.4 GHz obtains measured peak efficiencies of 73% and 71.9% at 0 dBm input, respectively. The buck–boost dc–dc converter employed in the proposed hybrid energy harvesting system achieves a measured peak PCE of 94.5%.

This paper presents a reconfigurable wide input power range radio frequency (RF) energy harvester (EH) with alliance for wireless power (A4WP) wireless power receiver (WPR). A reconfigurable RF-DC converter for RF EH and maximum power point tracking algorithm are proposed to maintain high efficiency over a wide input power range -20 to +20 dBm. The A4WP WPR is designed and merged with the EH to receive power higher than +20 dBm. In order to improve the power conversion efficiency (PCE), the delay between the ac input voltage and current is compensated by the proposed open-loop delay compensation method. The chip is implemented in 0.18 μm bipolar-CMOS-double-diffused metal-oxide-semiconductor process. The die area of the chip is 4.3 mm × 3.2 mm, including the pads. The proposed EH with WPR achieves a measured peak PCE of 48.19% with respect to the input power of 0 dBm at 900 MHz. It also has a peak PCE of 82.14% with respect to the input power of 30 dBm in an A4WP mode operation at 6.78 MHz.

An energy efficient, low-power 10-bit asynchronous successive approximation register (SAR) analog-to-digital (ADC) converter with the sampling frequency of 8 MS/s is presented in the proposed paper for IEEE 802.15.1 IoT sensor based applications. An improved common mode charge redistribution algorithm is proposed for binary weighted SAR ADC. The proposed method uses available VCM level for SAR ADC conversion, and this method reduces the switching power more than 12% without any additional DAC driver as compared to merged capacitor switching (MCS). Mathematical analysis of the proposed switching scheme results in the lower or equal power consumption for every digital code as compared to MCS. A two stage dynamic latched comparator with adaptive power control (APC) technique is used to optimize the overall efficiency. Furthermore, to minimize the digital part power consumption, a modified asynchronous SAR logic with digitally controlled delay cells is proposed. High efficiency with low power consumption makes it suitable for low power devices especially for IEEE 802.15.1 IoT sensor based applications. The proposed prototype is implemented using 1P6M 55 nm complementary metaloxide-semiconductor (CMOS) technology. The measurement results that the proposed circuit achieves are 9.3 effective number of bits (ENOB) with signal-to-noise and distortion ratio (SNDR) of 58.05 dB at a sampling rate of 8 MS/s. The power consumption of SAR ADC is 45 μW when operated at 1 V power supply. INDEX.