The effect of displacement defect on SiC metal-oxide-semiconductor field-effect transistors (MOSFETs) due to radiation is investigated using technology computer-aided design (TCAD) simulation. The position, energy level, and concentration of the displacement defect are considered as variables. The transfer characteristics, breakdown voltage, and energy loss of a double-pulse switching test circuit are analyzed. Compared with the shallow defect energy level, the deepest defect energy level with E_C − 1.55 eV exhibits considerable degradation. The on-current decreases by 54% and on-resistance increases by 293% due to the displacement defect generated at the parasitic junction field-effect transistor (JFET) region next to the P-well. Due to the existence of a defect in the drift region, the breakdown voltage increased up to 21 V. In the double-pulse switching test, the impact of displacement defect on the power loss of SiC MOSFETs is negligible.

Due to the aggressive scaling down of logic semiconductors, the difficulty of semiconductor component processes has increased. As the structure of components becomes more complex, the time and cost of processes and simulations have risen. Machine learning is now being used to analyze the electrical characteristics data of semiconductor components and apply the trained machine learning to next-generation semiconductor development. Machine learning trained on process data and simulation results can quickly and accurately predict which electrical characteristics change significantly when the component’s structure changes and which parameters have a significant impact on the electrical characteristic changes. This paper presents suitable machine learning models for analyzing and predicting the electrical characteristics (on-current ( I_on ), off-current ( I_off ), threshold voltage ( V_th ), subthreshold swing (SS), and drain induced barrier lowering (DIBL)) and statistical distribution (mean and standard deviation of the electrical characteristics) resulting from geometrical variability (sheet thickness ( T_wire ), sheet diameter ( D_wire ), oxide thickness ( T_ox ), gate length ( L_g ), spacer length ( L_sp ), gate metal work-function (WF)) in nanosheet field-effect transistor (NSFET), which are a next-generation logic device. Machine learning models, including regulation-based models (Ridge, LASSO) and tree-based models (decision tree (DT), random forest (RF), extreme gradient boost (XGBoost), and light gradient boost machine (LGBM)), are trained on technology computer-aided design (TCAD) simulation data. The LGBM more accurately predicts the electrical characteristics and statistical distribution of the NSFET than the other models. Additionally, we analyze the effect of geometrical variability on the NSFET based on feature importance.

Total ionizing dose (TID) effects of gamma rays were investigated on DDR4 dynamic random access memory (DRAM) and analyzed using TCAD simulations. In this study, we considered the operating states, dose rates, temperatures, and annealing to analyze the impact of TID under different conditions. The worst degradation was observed in the operated state and at a low-dose rate because of the absence of an electrostatic barrier that reduced the possibility of interface trap formation under unbiased and high-dose rate conditions. At lower temperatures, the effects of radiation were mitigated by the reduced production of protons (H ⁺ ). In addition, the unbiased DRAM and high-temperature conditions are the fastest to recover during post-irradiation annealing. In TCAD simulations, the retention time decreased with increasing temperature because the band-to-band tunneling (BTBT) generation increased. Furthermore, the retention time and row activation latency ( t _RCD ) degraded as the concentration of the interface traps increased. This is because the interface traps caused leakage currents and hindered the flow of electrons.

A novel memory cell transistor structure based on a saddle fin-based DRAM is presented for highly reliable operations. The overhang saddle fin (oss-fin) active structure is formed by two steps of etching of the fin; isotropic etching for the short side and anisotropic etching for the long side of the fin. The overhang sidewall fin structure results in the increase of retention time, decrease of isolation leakage current, increase of rowhammering tolerance, and increase of programming efficiency. A Technology Computer-Aided Design (TCAD) simulation study compares the overhang and the conventional saddle fin (s-fin) in terms of those reliability parameters. A lowered electric field underneath the storage node, a lowered passing gate coupling capacitance, and an elongated isolation leakage path are attributed to the reliability enhancements in the overhang saddle fin.

In this work, the effect of displacement defect (DD) owing to cosmic rays on six-transistor (6T) static random access memory (SRAM) with a 3 nm node nanosheet field-effect transistor (NSFET) is investigated using technology computer-aided design (TCAD) simulation. In order to comprehensively study the uncertainty of the radiation of NSFET 6T SRAM, the shape of the DD cluster cross-section and the transistor damaged by the DD in 6T SRAM are considered. Read static noise margin (RSNM) degradation (19 %) is the highest when the rectangular cross-section of the DD cluster (rectangular-DD cluster) is located in the pull-down1 (PD1) transistor. To mitigate the rectangular-DD cluster damage, we studied the variation in the DD cluster influence on the sheet shape and the source/drain (S/D) overlap length fluctuation. The sheet shape resulted in 2.3 % lower RSNM degradation in NS compared with nanowire (NW). Under the worst conditions (PD1 transistor damaged rectangular-DD cluster, NW structure), the S/D underlap structure showed 3.7 % lower RSNM degradation than the S/D overlap structure.

We comprehensively investigate displacement-defect-induced current and static noise margin variations in six-transistor (6T) static random access memory (SRAM) based on a 10 nm node fin field-effect transistor (FinFET) using technology computer-aided design (TCAD). Various defect cluster conditions and fin structures are considered as variables to estimate the worst-case scenario for displacement defects. The rectangular defect clusters capture more widely distributed charges at the fin top, reducing the on- and off-current. The read static noise margin (RSNM) is the most degraded in the pull-down transistor during the read operation. The increased fin width decreases the RSNM due to the gate field. The current per cross-sectional area increases when the fin height decreases, but the energy barrier lowering by the gate field is similar. Therefore, the reduced fin width and increased fin height structure suit the 10 nm node FinFET 6T SRAMs with high radiation hardness.