The effect of displacement defect on SiC metal-oxide-semiconductor field-effect transistors (MOSFETs) due to radiation is investigated using technology computer-aided design (TCAD) simulation. The position, energy level, and concentration of the displacement defect are considered as variables. The transfer characteristics, breakdown voltage, and energy loss of a double-pulse switching test circuit are analyzed. Compared with the shallow defect energy level, the deepest defect energy level with E_C − 1.55 eV exhibits considerable degradation. The on-current decreases by 54% and on-resistance increases by 293% due to the displacement defect generated at the parasitic junction field-effect transistor (JFET) region next to the P-well. Due to the existence of a defect in the drift region, the breakdown voltage increased up to 21 V. In the double-pulse switching test, the impact of displacement defect on the power loss of SiC MOSFETs is negligible.

In this study, we investigate a novel design for a saddle-fin-based dynamic random access memory (s-fin DRAM) aimed at mitigating the Rowhammer (RH) effect. This work involves modifying the doping scheme and employing technology computer-aided design (TCAD) simulations. We propose two distinct doping schemes to counteract the RH effect within adjacent memory cells: local substrate implant (LSI) and adjusting the depth of the storage node (SN). For s-fin DRAM with LSI, we introduce an additional implant into the substrate region adjacent to the shallow trench isolation (STI) near the end of the passing gate (PG). This additional implant creates a higher conduction band energy (CBE) area, thereby reducing the electron density drawn from the SN due to the strong electric field when the PG is activated. The simulation results demonstrate that this LSI approach mitigates the RH effect by 62.7% and slightly improves the retention time, primarily owing to the lowered gate work function. A significant improvement in RH tolerance up to 2.3 times greater than that for conventional s-fin DRAM is observed for s-fin DRAM with SN depth modification. This enhancement is attributed to the increased depth of the SN, which reduces the inversion area caused by PG activation, with the depletion area closely situated near the SN junction. Furthermore, we combine LSI approach with the s-fin DRAM design featuring an increased SN depth. The findings reveal that the designed s-fin DRAM exhibits up to 3.4 times greater RH tolerance than its conventional counterpart.

Due to the aggressive scaling down of logic semiconductors, the difficulty of semiconductor component processes has increased. As the structure of components becomes more complex, the time and cost of processes and simulations have risen. Machine learning is now being used to analyze the electrical characteristics data of semiconductor components and apply the trained machine learning to next-generation semiconductor development. Machine learning trained on process data and simulation results can quickly and accurately predict which electrical characteristics change significantly when the component’s structure changes and which parameters have a significant impact on the electrical characteristic changes. This paper presents suitable machine learning models for analyzing and predicting the electrical characteristics (on-current ( I_on ), off-current ( I_off ), threshold voltage ( V_th ), subthreshold swing (SS), and drain induced barrier lowering (DIBL)) and statistical distribution (mean and standard deviation of the electrical characteristics) resulting from geometrical variability (sheet thickness ( T_wire ), sheet diameter ( D_wire ), oxide thickness ( T_ox ), gate length ( L_g ), spacer length ( L_sp ), gate metal work-function (WF)) in nanosheet field-effect transistor (NSFET), which are a next-generation logic device. Machine learning models, including regulation-based models (Ridge, LASSO) and tree-based models (decision tree (DT), random forest (RF), extreme gradient boost (XGBoost), and light gradient boost machine (LGBM)), are trained on technology computer-aided design (TCAD) simulation data. The LGBM more accurately predicts the electrical characteristics and statistical distribution of the NSFET than the other models. Additionally, we analyze the effect of geometrical variability on the NSFET based on feature importance.

This study investigates the row hammer tolerance and potential degradation by capacitive crosstalk (CC) and parasitic bipolar junction transistor (BJT) effect in vertically stacked dynamic random-access memory (VS-DRAM) using technology computer-aided design (TCAD) simulations. The close arrangement of word lines in VS-DRAM results in a subthreshold leakage by the CC effect. Furthermore, as VS-DRAM has a floating body, hole accumulation in the body occurs via gate-induced drain leakage (GIDL) at the storage node in the cell that stores ‘1’. This can be accelerated by activating the bit line (BL). This causes leakage current ( I_BJT ) by the parasitic BJT when the BL state becomes low and it is found that I_BJT can be enhanced by the CC effect in this study. The row hammer effect and I_BJT by the CC and parasitic BJT effects can be mitigated by reducing Si width.

The effects of single event upset (SEU) by alpha particles and heavy ions on the data flip of a 3 nm technology node gate-all-around (GAA) nanosheet field-effect transistor (NSFET) 6T static random access memory (SRAM) cell was studied through technology computer-aided design (TCAD) simulations. It was found that the sensitivity to radiation in the “off” pull-down transistor varies depending on the position of the alpha particle and heavy ions in the incident. The most significant radiation-induced increase in electron density occurs at the drain–channel junction. Heavy ion strikes lead to the lowest threshold linear energy transfer ( LET_th ) value during the hold operation compared to read and write operations. The partial bottom dielectric isolation (PDI) scheme demonstrates lower radiation sensitivity than the conventional scheme, as the PDI layer acts as a physical barrier preventing charge migration from the substrate to the drain.

This paper presents a comprehensive review of the effects of radiation on advanced semiconductor devices. As device dimensions continue to scale into the nanometer regime, radiation vulnerability has emerged as a crucial reliability concern, particularly in state-of-the-art device architectures, such as nanosheet field-effect transistor (NSFETs), 3D NAND flash memory, and dynamic random access memory (DRAM). This review focuses on three major radiation effect mechanisms, namely displacement defect (DD), total ionizing dose (TID), and single event effects (SEE), encompassing single event transient (SET) and single event upset (SEU). We analyzed the physical origins and performance impacts of these mechanisms based on technology computer-aided design (TCAD) simulations. In particular, we examined the effects of DD, TID, and SET on NSFETs, and the SEU phenomena in NSFET-based 6-T SRAM, saddle-fin DRAM, and 3D charge-trap NAND flash memory. This review synthesizes recent advances in understanding radiation effects in modern nanoscale devices and emphasizes the importance of TCAD simulations in guiding the design and evaluation of future radiation-hardened technologies.